From patchwork Thu Dec 1 05:16:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 9455441 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8B15060235 for ; Thu, 1 Dec 2016 05:34:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7BDD9283E8 for ; Thu, 1 Dec 2016 05:34:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6CC8D2846D; Thu, 1 Dec 2016 05:34:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 07231283E8 for ; Thu, 1 Dec 2016 05:34:23 +0000 (UTC) Received: from localhost ([::1]:48238 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cCK0k-0002bv-49 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 01 Dec 2016 00:34:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cCJjw-0004o4-5C for qemu-devel@nongnu.org; Thu, 01 Dec 2016 00:17:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cCJju-0000LN-S5 for qemu-devel@nongnu.org; Thu, 01 Dec 2016 00:17:00 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53638) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cCJju-0000LF-JV for qemu-devel@nongnu.org; Thu, 01 Dec 2016 00:16:58 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AD79698C23; Thu, 1 Dec 2016 05:16:57 +0000 (UTC) Received: from weilaptop.redhat.com (vpn-61-59.rdu2.redhat.com [10.10.61.59]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uB15Ggrd016323; Thu, 1 Dec 2016 00:16:55 -0500 From: Wei Huang To: cov@codeaurora.org Date: Wed, 30 Nov 2016 23:16:41 -0600 Message-Id: <1480569402-8848-4-git-send-email-wei@redhat.com> In-Reply-To: <1480569402-8848-1-git-send-email-wei@redhat.com> References: <1480569402-8848-1-git-send-email-wei@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Thu, 01 Dec 2016 05:16:57 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v13 3/4] arm: pmu: Check cycle count increases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alindsay@codeaurora.org, drjones@redhat.com, kvm@vger.kernel.org, andre.przywara@arm.com, croberts@codeaurora.org, qemu-devel@nongnu.org, alistair.francis@xilinx.com, shannon.zhao@linaro.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Christopher Covington Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington Signed-off-by: Wei Huang Reviewed-by: Andrew Jones --- arm/pmu.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 1fe2b1a..3566a27 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -16,6 +16,9 @@ #include "asm/barrier.h" #include "asm/processor.h" +#define PMU_PMCR_E (1 << 0) +#define PMU_PMCR_C (1 << 2) +#define PMU_PMCR_LC (1 << 6) #define PMU_PMCR_N_SHIFT 11 #define PMU_PMCR_N_MASK 0x1f #define PMU_PMCR_ID_SHIFT 16 @@ -23,10 +26,57 @@ #define PMU_PMCR_IMP_SHIFT 24 #define PMU_PMCR_IMP_MASK 0xff +#define ID_DFR0_PERFMON_SHIFT 24 +#define ID_DFR0_PERFMON_MASK 0xf + +#define PMU_CYCLE_IDX 31 + +#define NR_SAMPLES 10 + +static unsigned int pmu_version; #if defined(__arm__) DEFINE_GET_SYSREG32(pmcr, 0, c9, c12, 0) +DEFINE_SET_SYSREG32(pmcr, 0, c9, c12, 0) +DEFINE_GET_SYSREG32(id_dfr0, 0, c0, c1, 2) +DEFINE_SET_SYSREG32(pmselr, 0, c9, c12, 5) +DEFINE_SET_SYSREG32(pmxevtyper, 0, c9, c13, 1) +DEFINE_GET_SYSREG32(pmccntr32, 0, c9, c13, 0) +DEFINE_SET_SYSREG32(pmccntr32, 0, c9, c13, 0) +DEFINE_GET_SYSREG64(pmccntr64, 0, c9) +DEFINE_SET_SYSREG64(pmccntr64, 0, c9) +DEFINE_SET_SYSREG32(pmcntenset, 0, c9, c12, 1) + +static inline uint64_t get_pmccntr(void) +{ + if (pmu_version == 0x3) + return get_pmccntr64(); + else + return get_pmccntr32(); +} + +static inline void set_pmccntr(uint64_t value) +{ + if (pmu_version == 0x3) + set_pmccntr64(value); + else + set_pmccntr32(value & 0xffffffff); +} + +/* PMCCFILTR is an obsolete name for PMXEVTYPER31 in ARMv7 */ +static inline void set_pmccfiltr(uint32_t value) +{ + set_pmselr(PMU_CYCLE_IDX); + set_pmxevtyper(value); + isb(); +} #elif defined(__aarch64__) DEFINE_GET_SYSREG32(pmcr, el0) +DEFINE_SET_SYSREG32(pmcr, el0) +DEFINE_GET_SYSREG32(id_dfr0, el1) +DEFINE_GET_SYSREG64(pmccntr, el0); +DEFINE_SET_SYSREG64(pmccntr, el0); +DEFINE_SET_SYSREG32(pmcntenset, el0); +DEFINE_SET_SYSREG32(pmccfiltr, el0); #endif /* @@ -52,11 +102,55 @@ static bool check_pmcr(void) return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0; } +/* + * Ensure that the cycle counter progresses between back-to-back reads. + */ +static bool check_cycles_increase(void) +{ + bool success = true; + + /* init before event access, this test only cares about cycle count */ + set_pmcntenset(1 << PMU_CYCLE_IDX); + set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ + set_pmccntr(0); + + set_pmcr(get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E); + + for (int i = 0; i < NR_SAMPLES; i++) { + uint64_t a, b; + + a = get_pmccntr(); + b = get_pmccntr(); + + if (a >= b) { + printf("Read %"PRId64" then %"PRId64".\n", a, b); + success = false; + break; + } + } + + set_pmcr(get_pmcr() & ~PMU_PMCR_E); + + return success; +} + +void pmu_init(void) +{ + uint32_t dfr0; + + /* probe pmu version */ + dfr0 = get_id_dfr0(); + pmu_version = (dfr0 >> ID_DFR0_PERFMON_SHIFT) & ID_DFR0_PERFMON_MASK; + report_info("PMU version: %d", pmu_version); +} + int main(void) { report_prefix_push("pmu"); + pmu_init(); report("Control register", check_pmcr()); + report("Monotonically increasing cycle count", check_cycles_increase()); return report_summary(); }