From patchwork Tue Dec 6 18:05:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 9463077 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 79DBC6022E for ; Tue, 6 Dec 2016 18:20:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6FE3928496 for ; Tue, 6 Dec 2016 18:20:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6269B284A0; Tue, 6 Dec 2016 18:20:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5533F28496 for ; Tue, 6 Dec 2016 18:20:04 +0000 (UTC) Received: from localhost ([::1]:33819 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cEKLT-0003Hl-CK for patchwork-qemu-devel@patchwork.kernel.org; Tue, 06 Dec 2016 13:20:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cEK7a-0006nn-6G for qemu-devel@nongnu.org; Tue, 06 Dec 2016 13:05:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cEK7Z-0005ZQ-24 for qemu-devel@nongnu.org; Tue, 06 Dec 2016 13:05:42 -0500 Received: from mx1.redhat.com ([209.132.183.28]:38254) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cEK7Y-0005Yl-PQ for qemu-devel@nongnu.org; Tue, 06 Dec 2016 13:05:40 -0500 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5D09B558B1; Tue, 6 Dec 2016 18:05:39 +0000 (UTC) Received: from weilaptop.redhat.com (vpn-62-139.rdu2.redhat.com [10.10.62.139]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uB6I5TOh002456; Tue, 6 Dec 2016 13:05:37 -0500 From: Wei Huang To: cov@codeaurora.org Date: Tue, 6 Dec 2016 12:05:27 -0600 Message-Id: <1481047528-16180-5-git-send-email-wei@redhat.com> In-Reply-To: <1481047528-16180-1-git-send-email-wei@redhat.com> References: <1481047528-16180-1-git-send-email-wei@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 06 Dec 2016 18:05:39 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v14 4/5] arm: pmu: Check cycle count increases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alindsay@codeaurora.org, drjones@redhat.com, kvm@vger.kernel.org, andre.przywara@arm.com, croberts@codeaurora.org, qemu-devel@nongnu.org, alistair.francis@xilinx.com, shannon.zhao@linaro.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Christopher Covington Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington Signed-off-by: Wei Huang --- arm/pmu.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index bf6ac69..d9ff19d 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -18,6 +18,9 @@ #include "asm/sysreg.h" #include "asm/processor.h" +#define PMU_PMCR_E (1 << 0) +#define PMU_PMCR_C (1 << 2) +#define PMU_PMCR_LC (1 << 6) #define PMU_PMCR_N_SHIFT 11 #define PMU_PMCR_N_MASK 0x1f #define PMU_PMCR_ID_SHIFT 16 @@ -28,16 +31,47 @@ #define ID_DFR0_PERFMON_SHIFT 24 #define ID_DFR0_PERFMON_MASK 0xf +#define PMU_CYCLE_IDX 31 + +#define NR_SAMPLES 10 + static unsigned int pmu_version; #if defined(__arm__) #define PMCR __ACCESS_CP15(c9, 0, c12, 0) #define ID_DFR0 __ACCESS_CP15(c0, 0, c1, 2) +#define PMSELR __ACCESS_CP15(c9, 0, c12, 5) +#define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1) +#define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1) +#define PMCCNTR32 __ACCESS_CP15(c9, 0, c13, 0) +#define PMCCNTR64 __ACCESS_CP15_64(0, c9) static inline uint32_t get_id_dfr0(void) { return read_sysreg(ID_DFR0); } static inline uint32_t get_pmcr(void) { return read_sysreg(PMCR); } +static inline void set_pmcr(uint32_t v) { write_sysreg(v, PMCR); } +static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, PMCNTENSET); } + +static inline uint64_t get_pmccntr(void) +{ + if (pmu_version == 0x3) + return read_sysreg(PMCCNTR64); + else + return read_sysreg(PMCCNTR32); +} + +/* PMCCFILTR is an obsolete name for PMXEVTYPER31 in ARMv7 */ +static inline void set_pmccfiltr(uint32_t value) +{ + write_sysreg(PMU_CYCLE_IDX, PMSELR); + write_sysreg(value, PMXEVTYPER); + isb(); +} #elif defined(__aarch64__) static inline uint32_t get_id_dfr0(void) { return read_sysreg(id_dfr0_el1); } static inline uint32_t get_pmcr(void) { return read_sysreg(pmcr_el0); } +static inline void set_pmcr(uint32_t v) { write_sysreg(v, pmcr_el0); } +static inline uint64_t get_pmccntr(void) { return read_sysreg(pmccntr_el0); } +static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, pmcntenset_el0); } +static inline void set_pmccfiltr(uint32_t v) { write_sysreg(v, pmccfiltr_el0); } #endif /* @@ -63,6 +97,37 @@ static bool check_pmcr(void) return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0; } +/* + * Ensure that the cycle counter progresses between back-to-back reads. + */ +static bool check_cycles_increase(void) +{ + bool success = true; + + /* init before event access, this test only cares about cycle count */ + set_pmcntenset(1 << PMU_CYCLE_IDX); + set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ + + set_pmcr(get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E); + + for (int i = 0; i < NR_SAMPLES; i++) { + uint64_t a, b; + + a = get_pmccntr(); + b = get_pmccntr(); + + if (a >= b) { + printf("Read %"PRId64" then %"PRId64".\n", a, b); + success = false; + break; + } + } + + set_pmcr(get_pmcr() & ~PMU_PMCR_E); + + return success; +} + /* Return FALSE if no PMU found, otherwise return TRUE */ bool pmu_probe(void) { @@ -88,6 +153,7 @@ int main(void) report_prefix_push("pmu"); report("Control register", check_pmcr()); + report("Monotonically increasing cycle count", check_cycles_increase()); return report_summary(); }