diff mbox

[03/11] target-ppc: Add xsiexpdp instruction

Message ID 1484038243-30314-4-git-send-email-nikunj@linux.vnet.ibm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Nikunj A. Dadhania Jan. 10, 2017, 8:50 a.m. UTC 
xsiexpdp: VSX Scalar Insert Exponent Double Precision

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target/ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
 target/ppc/translate/vsx-ops.inc.c  |  1 +
 2 files changed, 21 insertions(+)

Comments

David Gibson Jan. 12, 2017, 2:47 a.m. UTC | #1 
On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote:
> xsiexpdp: VSX Scalar Insert Exponent Double Precision
> 
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target/ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
>  target/ppc/translate/vsx-ops.inc.c  |  1 +
>  2 files changed, 21 insertions(+)
> 
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 2d9fe50..2d09225 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1243,6 +1243,26 @@ static void gen_xsxexpqp(DisasContext *ctx)
>      tcg_gen_movi_i64(xtl, 0);
>  }
>  
> +static void gen_xsiexpdp(DisasContext *ctx)
> +{
> +    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
> +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
> +    TCGv rb = cpu_gpr[rB(ctx->opcode)];
> +    TCGv_i64 t0;
> +
> +    if (unlikely(!ctx->vsx_enabled)) {
> +        gen_exception(ctx, POWERPC_EXCP_VSXU);
> +        return;
> +    }
> +    t0 = tcg_temp_new_i64();
> +    tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
> +    tcg_gen_andi_i64(t0, rb, 0x7FF);
> +    tcg_gen_shli_i64(t0, t0, 52);
> +    tcg_gen_or_i64(xth, xth, t0);
> +    /* dword[1] is undefined */

According to the ISA doc I have, dword[1] is set to 0 rather than
being undefined.

> +    tcg_temp_free_i64(t0);
> +}
> +
>  static void gen_xsxsigdp(DisasContext *ctx)
>  {
>      TCGv rt = cpu_gpr[rD(ctx->opcode)];
> diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
> index aeeaff2..5980ac6 100644
> --- a/target/ppc/translate/vsx-ops.inc.c
> +++ b/target/ppc/translate/vsx-ops.inc.c
> @@ -120,6 +120,7 @@ GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
>  GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
>  GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
>  GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
> +GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300),
>  #endif
>  
>  GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
Nikunj A. Dadhania Jan. 12, 2017, 4:53 a.m. UTC | #2 
David Gibson <david@gibson.dropbear.id.au> writes:

> [ Unknown signature status ]
> On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote:
>> xsiexpdp: VSX Scalar Insert Exponent Double Precision
>> 
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>>  target/ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
>>  target/ppc/translate/vsx-ops.inc.c  |  1 +
>>  2 files changed, 21 insertions(+)
>> 
>> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
>> index 2d9fe50..2d09225 100644
>> --- a/target/ppc/translate/vsx-impl.inc.c
>> +++ b/target/ppc/translate/vsx-impl.inc.c
>> @@ -1243,6 +1243,26 @@ static void gen_xsxexpqp(DisasContext *ctx)
>>      tcg_gen_movi_i64(xtl, 0);
>>  }
>>  
>> +static void gen_xsiexpdp(DisasContext *ctx)
>> +{
>> +    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
>> +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
>> +    TCGv rb = cpu_gpr[rB(ctx->opcode)];
>> +    TCGv_i64 t0;
>> +
>> +    if (unlikely(!ctx->vsx_enabled)) {
>> +        gen_exception(ctx, POWERPC_EXCP_VSXU);
>> +        return;
>> +    }
>> +    t0 = tcg_temp_new_i64();
>> +    tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
>> +    tcg_gen_andi_i64(t0, rb, 0x7FF);
>> +    tcg_gen_shli_i64(t0, t0, 52);
>> +    tcg_gen_or_i64(xth, xth, t0);
>> +    /* dword[1] is undefined */
>
> According to the ISA doc I have, dword[1] is set to 0 rather than
> being undefined.

Referring to xsiexpdp on page 570:

"The contents of doubleword element 1 of VSR[XT] are
undefined."

The revision that I have is dated November 30, 2015

Regards,
Nikunj
David Gibson Jan. 12, 2017, 5:11 a.m. UTC | #3 
On Thu, Jan 12, 2017 at 10:23:22AM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
> 
> > [ Unknown signature status ]
> > On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote:
> >> xsiexpdp: VSX Scalar Insert Exponent Double Precision
> >> 
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> ---
> >>  target/ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
> >>  target/ppc/translate/vsx-ops.inc.c  |  1 +
> >>  2 files changed, 21 insertions(+)
> >> 
> >> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> >> index 2d9fe50..2d09225 100644
> >> --- a/target/ppc/translate/vsx-impl.inc.c
> >> +++ b/target/ppc/translate/vsx-impl.inc.c
> >> @@ -1243,6 +1243,26 @@ static void gen_xsxexpqp(DisasContext *ctx)
> >>      tcg_gen_movi_i64(xtl, 0);
> >>  }
> >>  
> >> +static void gen_xsiexpdp(DisasContext *ctx)
> >> +{
> >> +    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
> >> +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
> >> +    TCGv rb = cpu_gpr[rB(ctx->opcode)];
> >> +    TCGv_i64 t0;
> >> +
> >> +    if (unlikely(!ctx->vsx_enabled)) {
> >> +        gen_exception(ctx, POWERPC_EXCP_VSXU);
> >> +        return;
> >> +    }
> >> +    t0 = tcg_temp_new_i64();
> >> +    tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
> >> +    tcg_gen_andi_i64(t0, rb, 0x7FF);
> >> +    tcg_gen_shli_i64(t0, t0, 52);
> >> +    tcg_gen_or_i64(xth, xth, t0);
> >> +    /* dword[1] is undefined */
> >
> > According to the ISA doc I have, dword[1] is set to 0 rather than
> > being undefined.
> 
> Referring to xsiexpdp on page 570:
> 
> "The contents of doubleword element 1 of VSR[XT] are
> undefined."
> 
> The revision that I have is dated November 30, 2015

Ah, sorry.  I think I just misread all those "U"s in the pseudo-code
as "0"s.  I'll blame the fact I'm using the little laptop screen,
since I've left my home office to escape the heat.
diff mbox

Patch

diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 2d9fe50..2d09225 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1243,6 +1243,26 @@  static void gen_xsxexpqp(DisasContext *ctx)
     tcg_gen_movi_i64(xtl, 0);
 }
 
+static void gen_xsiexpdp(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv ra = cpu_gpr[rA(ctx->opcode)];
+    TCGv rb = cpu_gpr[rB(ctx->opcode)];
+    TCGv_i64 t0;
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    t0 = tcg_temp_new_i64();
+    tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
+    tcg_gen_andi_i64(t0, rb, 0x7FF);
+    tcg_gen_shli_i64(t0, t0, 52);
+    tcg_gen_or_i64(xth, xth, t0);
+    /* dword[1] is undefined */
+    tcg_temp_free_i64(t0);
+}
+
 static void gen_xsxsigdp(DisasContext *ctx)
 {
     TCGv rt = cpu_gpr[rD(ctx->opcode)];
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index aeeaff2..5980ac6 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -120,6 +120,7 @@  GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
 GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
 GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
 GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
+GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300),
 #endif
 
 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),