From patchwork Fri Feb 10 05:25:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jitindar Singh X-Patchwork-Id: 9566007 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9FB53601EA for ; Fri, 10 Feb 2017 05:32:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8B1D72844A for ; Fri, 10 Feb 2017 05:32:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7E57F28544; Fri, 10 Feb 2017 05:32:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DB1B42844A for ; Fri, 10 Feb 2017 05:32:02 +0000 (UTC) Received: from localhost ([::1]:41926 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3oP-0002dP-Aq for patchwork-qemu-devel@patchwork.kernel.org; Fri, 10 Feb 2017 00:32:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3j4-0006Cs-Dl for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cc3j3-0001YH-2k for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:30 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:32818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cc3iy-0001WV-C9; Fri, 10 Feb 2017 00:26:24 -0500 Received: by mail-pg0-x244.google.com with SMTP id 194so2208259pgd.0; Thu, 09 Feb 2017 21:26:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PzhvIcrBi9btcPVpigl/k+BtcF450gg0JR7bQDRAdiY=; b=PgKXBN/1VjFTRqsDF0TA6UR4g/EPto7U6CcisGVwusxeTkwQ1EOlJxsQUw0xqV3IFN XjfHarfIHx28iFqBpNKwpduQ1NhsTICMn0VdSedZW1fl3hRv+/pit8cUQVcw5sz1B8k8 F7XdEKileziskdk/FW/aF4AAy33ju8aZc3qVxSkuHmUY8Udgju1jB9uwAyvpmmTdElK4 0v8aYtWbhtojShe9kL1rILEhqSoHJARh/kBRyvWTNSsvJEDpD0xPVKC/vZsqw6gwcqva +LDBdZqFThSIqoiU2CPGEIcWyOL/gzVj5iKJurkDPX072Efyj+LdZBdnhHHAdtEiWQQZ 1IHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PzhvIcrBi9btcPVpigl/k+BtcF450gg0JR7bQDRAdiY=; b=XRimpAm717Q4CylbBjXSdQYysS+mqiN87OpHltruoks3VDc25Ep0yv2du292B5EzPa y78DBuZgvg7/AGKlywjIqYyqzvvsAn9AcAUWXyocy9Vp15Dq4IYt/Ab0qXAq7MBLZjbH 9lNxsulQNFgYn5wa9qhs1n+vg4CK8e3Kw0G/Wqde6mTjex6HlgoR+SJr0c6gsRQ4mqdy sD3/3TFj1K6q7VT12gk/Sh++up+TS5zXt4vfwowEbNZaT5OA2edx9YEKe+mDuMAXJd+1 bb4uQXjyG0FxCU5KDDxtbFvfq8HoDi9f2J2Z6OA/z33KWPU2ihyFfD3HwCLuOZfA/qOX 48Tw== X-Gm-Message-State: AMke39nzpXqpODq34klbG9Nh7Yg1QJUTO71TFnX84uIDFrPzrAmASRCke5jLorK52n9mQQ== X-Received: by 10.84.139.195 with SMTP id 61mr9043305plr.116.1486704383586; Thu, 09 Feb 2017 21:26:23 -0800 (PST) Received: from surajjs.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id r78sm1308298pfl.63.2017.02.09.21.26.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 21:26:22 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:53 +1100 Message-Id: <1486704360-27361-4-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h | 18 ++++++++++++++++++ target/ppc/mmu-hash64.c | 8 ++++++++ target/ppc/translate_init.c | 24 ++++++++++++++++++------ 3 files changed, 44 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bb96dd5..425e79d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -384,12 +384,19 @@ struct ppc_slb_t { #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) #define LPCR_VRMASD_SHIFT (63 - 16) #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */ +#define LPCR_PECE_U_SHIFT (63 - 19) +#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) +#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */ #define LPCR_RMLS_SHIFT (63 - 37) #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) #define LPCR_ILE (1ull << (63 - 38)) #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) +#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */ +#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */ #define LPCR_ONL (1ull << (63 - 45)) +#define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */ #define LPCR_P7_PECE0 (1ull << (63 - 49)) #define LPCR_P7_PECE1 (1ull << (63 - 50)) #define LPCR_P7_PECE2 (1ull << (63 - 51)) @@ -398,11 +405,22 @@ struct ppc_slb_t { #define LPCR_P8_PECE2 (1ull << (63 - 49)) #define LPCR_P8_PECE3 (1ull << (63 - 50)) #define LPCR_P8_PECE4 (1ull << (63 - 51)) +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */ +#define LPCR_PECE_L_SHIFT (63 - 51) +#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT) +#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */ +#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */ +#define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable */ +#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable */ +#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable */ #define LPCR_MER (1ull << (63 - 52)) +#define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdown */ #define LPCR_TC (1ull << (63 - 54)) +#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Control */ #define LPCR_LPES0 (1ull << (63 - 60)) #define LPCR_LPES1 (1ull << (63 - 61)) #define LPCR_RMI (1ull << (63 - 62)) +#define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Enable */ #define LPCR_HDICE (1ull << (63 - 63)) #define msr_sf ((env->msr >> MSR_SF) & 1) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index bb78fb5..24d9901 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1050,6 +1050,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val) LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); break; + case POWERPC_MMU_3_00: /* P9 */ + lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); + break; default: ; } diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 84bf125..be35cbd 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8870,12 +8870,24 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu) lpcr->default_value &= ~LPCR_RMLS; lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT; - /* P7 and P8 has slightly different PECE bits, mostly because P8 adds - * bit 47 and 48 which are reserved on P7. Here we set them all, which - * will work as expected for both implementations - */ - lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | - LPCR_P8_PECE3 | LPCR_P8_PECE4; + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* By default we choose legacy mode and switch to new hash or radix + * when a register process table hcall is made. So disable process + * tables and guest translation shootdown by default + */ + lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE); + lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | + LPCR_OEE; + break; + default: + /* P7 and P8 has slightly different PECE bits, mostly because P8 adds + * bit 47 and 48 which are reserved on P7. Here we set them all, which + * will work as expected for both implementations + */ + lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; + } /* We should be followed by a CPU reset but update the active value * just in case...