From patchwork Thu Feb 16 00:27:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 9576021 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 70038600C5 for ; Thu, 16 Feb 2017 00:28:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6249D2857E for ; Thu, 16 Feb 2017 00:28:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5677828581; Thu, 16 Feb 2017 00:28:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BB4DE2857E for ; Thu, 16 Feb 2017 00:28:35 +0000 (UTC) Received: from localhost ([::1]:43600 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ce9w1-000897-KX for patchwork-qemu-devel@patchwork.kernel.org; Wed, 15 Feb 2017 19:28:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46480) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ce9vT-00088g-Rx for qemu-devel@nongnu.org; Wed, 15 Feb 2017 19:28:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ce9vR-0001FZ-DH for qemu-devel@nongnu.org; Wed, 15 Feb 2017 19:27:59 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:5697) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ce9vR-0001FD-8T for qemu-devel@nongnu.org; Wed, 15 Feb 2017 19:27:57 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 43C98B1D4E8B7; Thu, 16 Feb 2017 00:27:51 +0000 (GMT) Received: from localhost.localdomain (192.168.161.53) by hhmail02.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 16 Feb 2017 00:27:55 +0000 From: Yongbok Kim To: Date: Thu, 16 Feb 2017 00:27:23 +0000 Message-ID: <1487204850-16448-2-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1487204850-16448-1-git-send-email-yongbok.kim@imgtec.com> References: <1487204850-16448-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.161.53] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH v5 1/8] hw/mips_cmgcr: allow GCR base to be moved X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Burton , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Paul Burton Support moving the GCR base address & updating the CPU's CP0 CMGCRBase register appropriately. This is required if a platform needs to move its GCRs away from other memory, as the MIPS Boston development board does to avoid its flash memory. Signed-off-by: Paul Burton Reviewed-by: Leon Alrae Signed-off-by: Yongbok Kim --- hw/misc/mips_cmgcr.c | 17 +++++++++++++++++ include/hw/misc/mips_cmgcr.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index b3ba166..a1edb53 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -29,6 +29,20 @@ static inline bool is_gic_connected(MIPSGCRState *s) return s->gic_mr != NULL; } +static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val) +{ + CPUState *cpu; + MIPSCPU *mips_cpu; + + gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK; + memory_region_set_address(&gcr->iomem, gcr->gcr_base); + + CPU_FOREACH(cpu) { + mips_cpu = MIPS_CPU(cpu); + mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4; + } +} + static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val) { if (is_cpc_connected(gcr)) { @@ -117,6 +131,9 @@ static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other]; switch (addr) { + case GCR_BASE_OFS: + update_gcr_base(gcr, data); + break; case GCR_GIC_BASE_OFS: update_gic_base(gcr, data); break; diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h index a209d91..c9dfcb4 100644 --- a/include/hw/misc/mips_cmgcr.h +++ b/include/hw/misc/mips_cmgcr.h @@ -41,6 +41,9 @@ #define GCR_L2_CONFIG_BYPASS_SHF 20 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) +/* GCR_BASE register fields */ +#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL + /* GCR_GIC_BASE register fields */ #define GCR_GIC_BASE_GICEN_MSK 1 #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL