From patchwork Wed Mar 22 10:36:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cao jin X-Patchwork-Id: 9638431 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D0D2460327 for ; Wed, 22 Mar 2017 10:29:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B472A28306 for ; Wed, 22 Mar 2017 10:29:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A94A42841F; Wed, 22 Mar 2017 10:29:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 365A428306 for ; Wed, 22 Mar 2017 10:29:30 +0000 (UTC) Received: from localhost ([::1]:49952 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cqdWD-0002Or-Ad for patchwork-qemu-devel@patchwork.kernel.org; Wed, 22 Mar 2017 06:29:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cqdV5-0002ND-HH for qemu-devel@nongnu.org; Wed, 22 Mar 2017 06:28:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cqdV4-0007LA-Lq for qemu-devel@nongnu.org; Wed, 22 Mar 2017 06:28:19 -0400 Received: from [59.151.112.132] (port=24619 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cqdV4-0007Ju-9h for qemu-devel@nongnu.org; Wed, 22 Mar 2017 06:28:18 -0400 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="16863506" Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 22 Mar 2017 18:28:17 +0800 Received: from G08CNEXCHPEKD03.g08.fujitsu.local (unknown [10.167.33.85]) by cn.fujitsu.com (Postfix) with ESMTP id 9EAD347AD1FB; Wed, 22 Mar 2017 18:28:13 +0800 (CST) Received: from G08FNSTD140223.g08.fujitsu.local (10.167.226.69) by G08CNEXCHPEKD03.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 22 Mar 2017 18:28:13 +0800 From: Cao jin To: Date: Wed, 22 Mar 2017 18:36:50 +0800 Message-ID: <1490179012-14990-2-git-send-email-caoj.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1490179012-14990-1-git-send-email-caoj.fnst@cn.fujitsu.com> References: <1490179012-14990-1-git-send-email-caoj.fnst@cn.fujitsu.com> MIME-Version: 1.0 X-Originating-IP: [10.167.226.69] X-yoursite-MailScanner-ID: 9EAD347AD1FB.AFFF0 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: caoj.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v2 1/3] pcie aer: verify if AER functionality is available X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: izumi.taku@jp.fujitsu.com, alex.williamson@redhat.com, Dou Liyang , mst@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP For devices which support AER function, verify it can work or not in the system: 1. AER capable device is a PCIe device, it can't be plugged into PCI bus 2. If root port doesn't support AER, then there is no need to expose the AER capability Signed-off-by: Dou Liyang Signed-off-by: Cao jin --- hw/pci/pcie_aer.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index daf1f65..a2e9818 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -100,6 +100,34 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log) int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, uint16_t size, Error **errp) { + PCIDevice *parent_dev; + uint8_t type; + uint8_t parent_type; + + /* Topology test: see if there is need to expose AER cap */ + type = pcie_cap_get_type(dev); + parent_dev = pci_bridge_get_device(dev->bus); + while (parent_dev) { + parent_type = pcie_cap_get_type(parent_dev); + + if (type == PCI_EXP_TYPE_ENDPOINT && + (parent_type != PCI_EXP_TYPE_ROOT_PORT && + parent_type != PCI_EXP_TYPE_DOWNSTREAM)) { + error_setg(errp, "Parent device is not a PCIe component"); + return -ENOTSUP; + } + + if (parent_type == PCI_EXP_TYPE_ROOT_PORT) { + if (!parent_dev->exp.aer_cap) + { + error_setg(errp, "Root port does not support AER"); + return -ENOTSUP; + } + } + + parent_dev = pci_bridge_get_device(parent_dev->bus); + } + pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver, offset, size); dev->exp.aer_cap = offset;