From patchwork Wed Jun 28 14:13:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 9814381 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 718D460365 for ; Wed, 28 Jun 2017 14:15:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60AEF284F4 for ; Wed, 28 Jun 2017 14:15:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5346328509; Wed, 28 Jun 2017 14:15:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 20158284FE for ; Wed, 28 Jun 2017 14:15:01 +0000 (UTC) Received: from localhost ([::1]:33618 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDkC-00022w-6y for patchwork-qemu-devel@patchwork.kernel.org; Wed, 28 Jun 2017 10:15:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDj9-0001OO-Qo for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:14:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDj6-0001uf-Ka for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:13:55 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:58096) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDj6-0001uO-4G; Wed, 28 Jun 2017 10:13:52 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SEDmSA028906; Wed, 28 Jun 2017 16:13:48 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id B792117D; Wed, 28 Jun 2017 16:13:42 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 17:13:41 +0300 Message-Id: <149865922142.17063.17637554632892697681.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SEDmSA028906 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 29/29] target/arm: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Lluís Vilanova --- target/arm/translate-a64.c | 125 +++++++------------------------------------- target/arm/translate.c | 124 +++++++------------------------------------- target/arm/translate.h | 8 --- 3 files changed, 42 insertions(+), 215 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cc8bbb2b44..84d32ca547 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11250,6 +11250,14 @@ static void aarch64_trblock_init_disas_context(DisasContextBase *dcbase, init_tmp_a64_array(dc); } +static void aarch64_trblock_init_globals(DisasContextBase *db, CPUState *cpu) +{ +} + +static void aarch64_trblock_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void aarch64_trblock_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -11377,6 +11385,9 @@ static void aarch64_trblock_tb_stop(DisasContextBase *dcbase, CPUState *cpu) break; } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next = dc->pc; } static void aarch64_trblock_disas_log(const DisasContextBase *dcbase, @@ -11389,107 +11400,13 @@ static void aarch64_trblock_disas_log(const DisasContextBase *dcbase, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) -{ - DisasContext *dc = container_of(dcbase, DisasContext, base); - int max_insns; - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; - aarch64_trblock_init_disas_context(&dc->base, cs); - - max_insns = dc->base.tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - - do { - dc->base.num_insns++; - aarch64_trblock_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - BreakpointCheckType bp_check = - aarch64_trblock_breakpoint_check(&dc->base, cs, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - dc->base.pc_next = aarch64_trblock_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled || - singlestep || dc->base.num_insns >= max_insns)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - */ - } while (!dc->base.is_jmp); - - aarch64_trblock_tb_stop(&dc->base, cs); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - -done_generating: - gen_tb_end(tb, dc->base.num_insns); - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - aarch64_trblock_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif - dc->base.tb->size = dc->pc - dc->base.pc_first; - dc->base.tb->icount = dc->base.num_insns; -} +const TranslatorOps aarch64_translator_ops = { + .init_disas_context = aarch64_trblock_init_disas_context, + .init_globals = aarch64_trblock_init_globals, + .tb_start = aarch64_trblock_tb_start, + .insn_start = aarch64_trblock_insn_start, + .breakpoint_check = aarch64_trblock_breakpoint_check, + .translate_insn = aarch64_trblock_translate_insn, + .tb_stop = aarch64_trblock_tb_stop, + .disas_log = aarch64_trblock_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index 30dacee139..323cbac672 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12136,6 +12136,9 @@ static void arm_trblock_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_goto_tb(dc, 1, dc->pc); } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next = dc->pc; } static void arm_trblock_disas_log(const DisasContextBase *dcbase, CPUState *cpu) @@ -12147,116 +12150,29 @@ static void arm_trblock_disas_log(const DisasContextBase *dcbase, CPUState *cpu) dc->thumb | (dc->sctlr_b << 1)); } +static const TranslatorOps arm_translator_ops = { + .init_disas_context = arm_trblock_init_disas_context, + .init_globals = arm_trblock_init_globals, + .tb_start = arm_trblock_tb_start, + .insn_start = arm_trblock_insn_start, + .breakpoint_check = arm_trblock_breakpoint_check, + .translate_insn = arm_trblock_translate_insn, + .tb_stop = arm_trblock_tb_stop, + .disas_log = arm_trblock_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc1, *dc = &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cpu, tb); - return; - } - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cpu->singlestep_enabled; - arm_trblock_init_disas_context(&dc->base, cpu); - - arm_trblock_init_globals(&dc->base, cpu); - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_trblock_tb_start(&dc->base, cpu); - - do { - dc->base.num_insns++; - arm_trblock_insn_start(&dc->base, cpu); - - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - BreakpointCheckType bp_check = - arm_trblock_breakpoint_check(&dc->base, cpu, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - dc->base.pc_next = arm_trblock_translate_insn(&dc->base, cpu); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >= max_insns)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - arm_trblock_tb_stop(&dc->base, cpu); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - -done_generating: - gen_tb_end(tb, dc->base.num_insns); - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - arm_trblock_disas_log(&dc->base, cpu); - qemu_log("\n"); - qemu_log_unlock(); - } + translate_block( +#ifdef TARGET_AARCH64 + ARM_TBFLAG_AARCH64_STATE(tb->flags) ? + &aarch64_translator_ops : #endif - tb->size = dc->pc - dc->base.pc_first; - tb->icount = dc->base.num_insns; + &arm_translator_ops, + &dc->base, cpu, tb); } static const char *cpu_mode_names[16] = { diff --git a/target/arm/translate.h b/target/arm/translate.h index f830775540..f0912ecc96 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -155,21 +155,15 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } -static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { }