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[178.140.16.138]) by smtp.gmail.com with ESMTPSA id s134sm1604053lfe.27.2017.07.22.15.12.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:12:14 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sun, 23 Jul 2017 01:11:49 +0300 Message-Id: <1500761510-1556-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761510-1556-1-git-send-email-zuban32s@gmail.com> References: <1500761510-1556-1-git-send-email-zuban32s@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [RFC PATCH v2 3/4] pci: add QEMU-specific PCI capability structure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: konrad.wilk@oracle.com, mst@redhat.com, qemu-devel@nongnu.org, Aleksandr Bezzubikov , kevin@koconnor.net, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Sizes of limits match ones from PCI Type 1 Configuration Space Header, number of buses to reserve occupies only 1 byte since it is the size of Subordinate Bus Number register. Signed-off-by: Aleksandr Bezzubikov --- src/hw/pci_cap.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 src/hw/pci_cap.h diff --git a/src/hw/pci_cap.h b/src/hw/pci_cap.h new file mode 100644 index 0000000..1382b0b --- /dev/null +++ b/src/hw/pci_cap.h @@ -0,0 +1,23 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +struct vendor_pci_cap { + u8 id; + u8 next; + u8 len; +}; + +struct redhat_pci_bridge_cap { + struct vendor_pci_cap hdr; + u8 bus_res; + u32 pref_lim_upper; + u16 pref_lim; + u16 mem_lim; + u16 io_lim_upper; + u8 io_lim; + u8 padd; +}; + +#endif /* _PCI_CAP_H */