From patchwork Sun Sep 17 17:15:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 9954965 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BAFE5603F2 for ; Sun, 17 Sep 2017 17:20:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A3F2228A76 for ; Sun, 17 Sep 2017 17:20:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 98E3F28A89; Sun, 17 Sep 2017 17:20:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 287B928A8D for ; Sun, 17 Sep 2017 17:20:25 +0000 (UTC) Received: from localhost ([::1]:33097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdEy-00009j-5c for patchwork-qemu-devel@patchwork.kernel.org; Sun, 17 Sep 2017 13:20:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdAy-00065L-La for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAt-0006A9-My for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:12 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39951 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAt-000695-GO; Sun, 17 Sep 2017 13:16:07 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAv-0005RD-63; Sun, 17 Sep 2017 18:16:10 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:44 +0100 Message-Id: <1505668548-16616-5-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 4/8] macio: convert pmac_ide_ops from old_mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Mark Cave-Ayland --- hw/ide/macio.c | 154 +++++++++++++++++++++----------------------------------- 1 file changed, 56 insertions(+), 98 deletions(-) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index db5db39..428fbfc 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -255,131 +255,89 @@ static void pmac_ide_flush(DBDMA_io *io) } /* PowerMac IDE memory IO */ -static void pmac_ide_writeb (void *opaque, - hwaddr addr, uint32_t val) +static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size) { MACIOIDEState *d = opaque; + uint64_t retval; + addr = (addr & 0xfff) >> 4; - addr = (addr & 0xFFF) >> 4; switch (addr) { - case 1 ... 7: - ide_ioport_write(&d->bus, addr, val); - break; - case 8: - case 22: - ide_cmd_write(&d->bus, 0, val); - break; - default: + case 0x0: + if (size == 2) { + retval = ide_data_readw(&d->bus, 0); + } else if (size == 4) { + retval = ide_data_readl(&d->bus, 0); + } else { + retval = 0xffffffff; + } break; - } -} - -static uint32_t pmac_ide_readb (void *opaque,hwaddr addr) -{ - uint8_t retval; - MACIOIDEState *d = opaque; - - addr = (addr & 0xFFF) >> 4; - switch (addr) { - case 1 ... 7: + case 0x1 ... 0x7: retval = ide_ioport_read(&d->bus, addr); break; - case 8: - case 22: + case 0x8: + case 0x16: retval = ide_status_read(&d->bus, 0); break; + case 0x20: + retval = d->timing_reg; + break; + case 0x30: + /* This is an interrupt state register that only exists + * in the KeyLargo and later variants. Bit 0x8000_0000 + * latches the DMA interrupt and has to be written to + * clear. Bit 0x4000_0000 is an image of the disk + * interrupt. MacOS X relies on this and will hang if + * we don't provide at least the disk interrupt + */ + retval = d->irq_reg; + break; default: - retval = 0xFF; + retval = 0xffffffff; break; } - return retval; -} - -static void pmac_ide_writew (void *opaque, - hwaddr addr, uint32_t val) -{ - MACIOIDEState *d = opaque; - - addr = (addr & 0xFFF) >> 4; - val = bswap16(val); - if (addr == 0) { - ide_data_writew(&d->bus, 0, val); - } -} -static uint32_t pmac_ide_readw (void *opaque,hwaddr addr) -{ - uint16_t retval; - MACIOIDEState *d = opaque; - - addr = (addr & 0xFFF) >> 4; - if (addr == 0) { - retval = ide_data_readw(&d->bus, 0); - } else { - retval = 0xFFFF; - } - retval = bswap16(retval); return retval; } -static void pmac_ide_writel (void *opaque, - hwaddr addr, uint32_t val) + +static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) { MACIOIDEState *d = opaque; + addr = (addr & 0xfff) >> 4; - addr = (addr & 0xFFF) >> 4; - val = bswap32(val); - if (addr == 0) { - ide_data_writel(&d->bus, 0, val); - } else if (addr == 0x20) { + switch (addr) { + case 0x0: + if (size == 2) { + ide_data_writew(&d->bus, 0, val); + } else if (size == 4) { + ide_data_writel(&d->bus, 0, val); + } + break; + case 0x1 ... 0x7: + ide_ioport_write(&d->bus, addr, val); + break; + case 0x8: + case 0x16: + ide_cmd_write(&d->bus, 0, val); + break; + case 0x20: d->timing_reg = val; - } else if (addr == 0x30) { + break; + case 0x30: if (val & 0x80000000u) { d->irq_reg &= 0x7fffffff; } + break; } } -static uint32_t pmac_ide_readl (void *opaque,hwaddr addr) -{ - uint32_t retval; - MACIOIDEState *d = opaque; - - addr = (addr & 0xFFF) >> 4; - if (addr == 0) { - retval = ide_data_readl(&d->bus, 0); - } else if (addr == 0x20) { - retval = d->timing_reg; - } else if (addr == 0x30) { - /* This is an interrupt state register that only exists - * in the KeyLargo and later variants. Bit 0x8000_0000 - * latches the DMA interrupt and has to be written to - * clear. Bit 0x4000_0000 is an image of the disk - * interrupt. MacOS X relies on this and will hang if - * we don't provide at least the disk interrupt - */ - retval = d->irq_reg; - } else { - retval = 0xFFFFFFFF; - } - retval = bswap32(retval); - return retval; -} - static const MemoryRegionOps pmac_ide_ops = { - .old_mmio = { - .write = { - pmac_ide_writeb, - pmac_ide_writew, - pmac_ide_writel, - }, - .read = { - pmac_ide_readb, - pmac_ide_readw, - pmac_ide_readl, - }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, + .read = pmac_ide_read, + .write = pmac_ide_write, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .endianness = DEVICE_LITTLE_ENDIAN, }; static const VMStateDescription vmstate_pmac = {