From patchwork Tue Dec 19 05:38:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 10122507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BCFD460390 for ; Tue, 19 Dec 2017 05:48:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE6292904E for ; Tue, 19 Dec 2017 05:48:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A2E552905A; Tue, 19 Dec 2017 05:48:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, FROM_LOCAL_NOVOWEL, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 27DA42904E for ; Tue, 19 Dec 2017 05:48:12 +0000 (UTC) Received: from localhost ([::1]:50667 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eRAl9-0008BE-B6 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 19 Dec 2017 00:48:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49594) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eRAdG-00016j-L5 for qemu-devel@nongnu.org; Tue, 19 Dec 2017 00:40:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eRAdF-00021o-EV for qemu-devel@nongnu.org; Tue, 19 Dec 2017 00:40:02 -0500 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:33490) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eRAdF-00021Q-5o for qemu-devel@nongnu.org; Tue, 19 Dec 2017 00:40:01 -0500 Received: by mail-wr0-x241.google.com with SMTP id v21so6296925wrc.0 for ; Mon, 18 Dec 2017 21:40:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8XssAmsPtSwy/sNGow+1xd4uOUwRv10SbSUalnQPePw=; b=XBSkD5Y6LXiQaUDTNqDSNDhQP95drCYA3wwRIB2cppt/abHrUXlJLK9SHeSNXTHRLU lxb3PArlvSUYZeCMHVFkWDw1uxY43Pz7Uj/Hd1uSwroqvGBc81ngQH2SxOLZBJYhl7qP eJzQ4YWHFUp/S1aSPL6Z7OYBueet9Um6zRkrvvO83PZm8wP0RFKmd3D34blGOQ4RQMKP Hhkor1f3aMp1TE8XSNunEZmd8icHt6L2t2wFFAyp1jfnjVNGRjxgvZfyCWLYPfCVQBsU Y/XBJ2XqpObK3fkxjolyD0hbchmy7DEtFUz3WImkFvTResOa2TP6o40hcwvaAenMEf37 efXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8XssAmsPtSwy/sNGow+1xd4uOUwRv10SbSUalnQPePw=; b=eJ3CFdCuSAGbHeA/odoViAarp6/8otk01Fse0jOdbFMpEbAeYxSWR5+mW5wFYrarsW DehLwYHnXly2OO7mVfwg2WUGnErg+FJk5Tf4tdE9+qiguC5Adfa/g2yYRlKyaaakN5cP VzYmHFWcQKD1ZuWyMSQbDADWFT+wLBrTGOoNiDlsWUTT0ZhLoRKQuhaFYvTjCTFz+UPs 7QOFJmQPJqHd/AseZOhUNEBApJUxFt20SWUxCahaJr17CA/lHMwNspZjD5Ac6WtD3nhv 5fyVIPkd7rfGSDOhhmBpl+0mxFIISfq5jXizOn07jvqXPhSZ5YNJaSqfC3rGG7g1LbVB GFww== X-Gm-Message-State: AKGB3mIM5CumtqcuWJNlgUa6jkmum/ligurzWb/mLSQIStN6c6Un3irS pgXbxqKPhpH2mm3Pjq9kePF41g== X-Google-Smtp-Source: ACJfBothB3FxfOH1yr+Ocs5JfDLNVrafmVK8RbyWL8ccL4KFOTuNQPFQEmkqgTqsPWyJq8JYQDXq8w== X-Received: by 10.25.84.21 with SMTP id i21mr1216219lfb.108.1513661999970; Mon, 18 Dec 2017 21:39:59 -0800 (PST) Received: from octofox.net (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id f67sm673187lfb.83.2017.12.18.21.39.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Dec 2017 21:39:59 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 21:38:48 -0800 Message-Id: <1513661932-6849-13-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1513661932-6849-1-git-send-email-jcmvbkbc@gmail.com> References: <1513661932-6849-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v2 12/16] target/xtensa: add internal/noop SRs and opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 2 ++ target/xtensa/translate.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e93bbb3c6d1e..80e9b47e84e9 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -127,6 +127,7 @@ enum { WINDOW_BASE = 72, WINDOW_START = 73, PTEVADDR = 83, + MMID = 89, RASID = 90, ITLBCFG = 91, DTLBCFG = 92, @@ -134,6 +135,7 @@ enum { MEMCTL = 97, CACHEATTR = 98, ATOMCTL = 99, + DDR = 104, IBREAKA = 128, DBREAKA = 144, DBREAKC = 160, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index fb6a4c979590..f644d9fed22a 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -135,6 +135,7 @@ static const XtensaReg sregnames[256] = { [WINDOW_START] = XTENSA_REG("WINDOW_START", XTENSA_OPTION_WINDOWED_REGISTER), [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), + [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), @@ -142,6 +143,7 @@ static const XtensaReg sregnames[256] = { [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), + [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), @@ -2767,6 +2769,12 @@ static const XtensaOpcodeOps core_ops[] = { .name = "extw", .translate = translate_nop, }, { + .name = "hwwdtlba", + .translate = translate_ill, + }, { + .name = "hwwitlba", + .translate = translate_ill, + }, { .name = "idtlb", .translate = translate_itlb, .par = (const uint32_t[]){true}, @@ -2852,6 +2860,9 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_mac16, .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, }, { + .name = "ldpte", + .translate = translate_ill, + }, { .name = "loop", .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_NEVER}, @@ -3270,9 +3281,15 @@ static const XtensaOpcodeOps core_ops[] = { .name = "retw.n", .translate = translate_retw, }, { + .name = "rfdd", + .translate = translate_ill, + }, { .name = "rfde", .translate = translate_rfde, }, { + .name = "rfdo", + .translate = translate_ill, + }, { .name = "rfe", .translate = translate_rfe, }, { @@ -3373,6 +3390,10 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_rsr, .par = (const uint32_t[]){DBREAKC + 1}, }, { + .name = "rsr.ddr", + .translate = translate_rsr, + .par = (const uint32_t[]){DDR}, + }, { .name = "rsr.debugcause", .translate = translate_rsr, .par = (const uint32_t[]){DEBUGCAUSE}, @@ -3808,6 +3829,10 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wsr, .par = (const uint32_t[]){DBREAKC + 1}, }, { + .name = "wsr.ddr", + .translate = translate_wsr, + .par = (const uint32_t[]){DDR}, + }, { .name = "wsr.debugcause", .translate = translate_wsr, .par = (const uint32_t[]){DEBUGCAUSE}, @@ -4000,6 +4025,10 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wsr, .par = (const uint32_t[]){MISC + 3}, }, { + .name = "wsr.mmid", + .translate = translate_wsr, + .par = (const uint32_t[]){MMID}, + }, { .name = "wsr.prid", .translate = translate_wsr, .par = (const uint32_t[]){PRID}, @@ -4127,6 +4156,10 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_xsr, .par = (const uint32_t[]){DBREAKC + 1}, }, { + .name = "xsr.ddr", + .translate = translate_xsr, + .par = (const uint32_t[]){DDR}, + }, { .name = "xsr.debugcause", .translate = translate_xsr, .par = (const uint32_t[]){DEBUGCAUSE},