| Message ID | 1529897961-134132-3-git-send-email-robert.hu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 25/06/2018 05:39, Robert Hoo wrote: > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as > SPEC_CTRL. > > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 1e69e68..3134af4 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -896,7 +896,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > NULL, NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > NULL, NULL, "spec-ctrl", NULL, > - NULL, NULL, NULL, "ssbd", > + NULL, "arch-capabilities", NULL, "ssbd", > }, > .cpuid_eax = 7, > .cpuid_needs_ecx = true, .cpuid_ecx = 0, > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 734a73e..1ef2040 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ > #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ > #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ > +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of RDCL_NO and IBRS_ALL*/ > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ > For migration to work, you need to add new "features" corresponding to the bits in the MSR, and include them in the Icelake-Server and Icelake-Client models. Unfortunately there is no code for this in QEMU yet, though the API is there in KVM. I have just sent the KVM patch to pass the MSR value down to QEMU ("KVM: VMX: support MSR_IA32_ARCH_CAPABILITIES as a feature MSR"). Paolo
On Mon, 2018-06-25 at 14:06 +0200, Paolo Bonzini wrote: > On 25/06/2018 05:39, Robert Hoo wrote: > > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as > > SPEC_CTRL. > > > > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> > > --- > > target/i386/cpu.c | 2 +- > > target/i386/cpu.h | 1 + > > 2 files changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index 1e69e68..3134af4 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -896,7 +896,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > > NULL, NULL, NULL, NULL, > > NULL, NULL, NULL, NULL, > > NULL, NULL, "spec-ctrl", NULL, > > - NULL, NULL, NULL, "ssbd", > > + NULL, "arch-capabilities", NULL, "ssbd", > > }, > > .cpuid_eax = 7, > > .cpuid_needs_ecx = true, .cpuid_ecx = 0, > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > > index 734a73e..1ef2040 100644 > > --- a/target/i386/cpu.h > > +++ b/target/i386/cpu.h > > @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > > #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ > > #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ > > #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ > > +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of RDCL_NO and IBRS_ALL*/ > > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > > > #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ > > > > For migration to work, you need to add new "features" corresponding to > the bits in the MSR, and include them in the Icelake-Server and > Icelake-Client models. Unfortunately there is no code for this in QEMU > yet, though the API is there in KVM. > > I have just sent the KVM patch to pass the MSR value down to QEMU ("KVM: > VMX: support MSR_IA32_ARCH_CAPABILITIES as a feature MSR"). > Thanks Paolo. > Paolo
On Mon, Jun 25, 2018 at 02:06:15PM +0200, Paolo Bonzini wrote: > On 25/06/2018 05:39, Robert Hoo wrote: > > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as > > SPEC_CTRL. > > > > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> > > --- > > target/i386/cpu.c | 2 +- > > target/i386/cpu.h | 1 + > > 2 files changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index 1e69e68..3134af4 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -896,7 +896,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > > NULL, NULL, NULL, NULL, > > NULL, NULL, NULL, NULL, > > NULL, NULL, "spec-ctrl", NULL, > > - NULL, NULL, NULL, "ssbd", > > + NULL, "arch-capabilities", NULL, "ssbd", > > }, > > .cpuid_eax = 7, > > .cpuid_needs_ecx = true, .cpuid_ecx = 0, > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > > index 734a73e..1ef2040 100644 > > --- a/target/i386/cpu.h > > +++ b/target/i386/cpu.h > > @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > > #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ > > #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ > > #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ > > +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of RDCL_NO and IBRS_ALL*/ > > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > > > #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ > > > > For migration to work, you need to add new "features" corresponding to > the bits in the MSR, and include them in the Icelake-Server and > Icelake-Client models. Unfortunately there is no code for this in QEMU > yet, though the API is there in KVM. Will all Icelake VCPUs of a given model have the same value on MSR_IA32_ARCH_CAPABILITIES? If not, we can't choose a value that will work on all cases, and it will require management software to be smarter and explicitly configure some of the MSR bits on the command-line.
On 28/06/2018 20:30, Eduardo Habkost wrote: >> For migration to work, you need to add new "features" corresponding to >> the bits in the MSR, and include them in the Icelake-Server and >> Icelake-Client models. Unfortunately there is no code for this in QEMU >> yet, though the API is there in KVM. > Will all Icelake VCPUs of a given model have the same value on > MSR_IA32_ARCH_CAPABILITIES? > > If not, we can't choose a value that will work on all cases, and > it will require management software to be smarter and explicitly > configure some of the MSR bits on the command-line. We can expect that it will change as more vulnerabilities are found and more microcode updates are issued. We should get it right from the beginning. Paolo
On Fri, Jun 29, 2018 at 01:34:04PM +0200, Paolo Bonzini wrote: > On 28/06/2018 20:30, Eduardo Habkost wrote: > >> For migration to work, you need to add new "features" corresponding to > >> the bits in the MSR, and include them in the Icelake-Server and > >> Icelake-Client models. Unfortunately there is no code for this in QEMU > >> yet, though the API is there in KVM. > > Will all Icelake VCPUs of a given model have the same value on > > MSR_IA32_ARCH_CAPABILITIES? > > > > If not, we can't choose a value that will work on all cases, and > > it will require management software to be smarter and explicitly > > configure some of the MSR bits on the command-line. > > We can expect that it will change as more vulnerabilities are found and > more microcode updates are issued. We should get it right from the > beginning. Right. Also, we probably want to enable arch-capabilities on CPUID by default whenever possible, even if using an old CPU model. I expect Daniel's versioned CPU model proposal to help us address this. I'm worried about the soft freeze deadline (next Tuesday), though. I wouldn't like Icelake to miss QEMU 3.0 just because we couldn't decide on a default MSR_IA32_ARCH_CAPABILITIES value in time.
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1e69e68..3134af4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -896,7 +896,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, "ssbd", + NULL, "arch-capabilities", NULL, "ssbd", }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 734a73e..1ef2040 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of RDCL_NO and IBRS_ALL*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)