| Message ID | 1530695199-27601-3-git-send-email-robert.hu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 04/07/2018 11:06, Robert Hoo wrote: > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as > SPEC_CTRL. > > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index b0b87c3..7f787ef 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1000,7 +1000,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > NULL, NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > NULL, NULL, "spec-ctrl", NULL, > - NULL, NULL, NULL, "ssbd", > + NULL, "arch-capabilities", NULL, "ssbd", > }, > .cpuid_eax = 7, > .cpuid_needs_ecx = true, .cpuid_ecx = 0, > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index ae97005..c2b297b 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -690,6 +690,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ > #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ > #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ > +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ > Doing this without the MSR is wrong. We need to leave it out of Icelake-Client/Icelake-Server. Eduardo, should the models be marked as non-migratable until it is in place? Paolo
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b0b87c3..7f787ef 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1000,7 +1000,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, "ssbd", + NULL, "arch-capabilities", NULL, "ssbd", }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ae97005..c2b297b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -690,6 +690,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)