From patchwork Wed Oct 3 15:07:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 10625023 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C85D15A7 for ; Wed, 3 Oct 2018 15:15:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5490828E62 for ; Wed, 3 Oct 2018 15:15:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 488C728E86; Wed, 3 Oct 2018 15:15:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CD3FF28E58 for ; Wed, 3 Oct 2018 15:15:16 +0000 (UTC) Received: from localhost ([::1]:49266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7irr-0003id-K7 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 03 Oct 2018 11:15:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48806) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7iqC-0002A4-29 for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:13:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7iq9-0006UC-4V for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:13:32 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:46148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7iq8-0006TT-U2; Wed, 03 Oct 2018 11:13:29 -0400 Received: by mail-pg1-x544.google.com with SMTP id a5-v6so1693023pgv.13; Wed, 03 Oct 2018 08:13:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9Ay3M6y+W3ArY+Q25A5a/bdjSssGSlE2NegpVjfAXco=; b=ZhV3lT0DoIRREMxrlgiqx+ThzbpVhLiiP5xO5V5lPhgYIADZ2hrOu9dsCUWf2yEIqY /nEIcomqj3Ft1X2k5S3OGXb7VPSPIFGuAy4oW2JiHhHzxVspK93xDOCe5J9TApEYd20i vv67Jvpytvz7MDKT5Ai3aKI8oEgeFg98XdCkwn4yoKFQBuX9rZOk6TaPYFz21SRXTCX8 /znzlFDfobqpmBkQpBtKC04duyXwG7H4kPxkjYKsYQAhAzKjWhk6+GiibKfSJ/9tbIpm QVJNyZCkdjUMowgMd3i6nXf2NARJ91i+5MoBQ2WMSdGHuGTg2NuTNNZKiD8WkmEaVnkj 8hHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9Ay3M6y+W3ArY+Q25A5a/bdjSssGSlE2NegpVjfAXco=; b=W9XTocd39ctlnrsNwThAuZ/lXEzRggQSdqTCuJp8MtWwB2ciiKfzaD2eHtkdqRQBQr eZVahGFNeceqD5Z1VcIq+DR1mBKGLk0eYo4OOW0oczVR3k0oZblxO2x9bjME5ctw2pzN V+3FpAjWVcmm4SdVtkB8jZ6kIZUdFKN+vpfU6BWIQerUKmXrM7DRkYx+gSWL7JiwH89m /Y0Y32E4YRMER+XnCIhfuGVeTP3BgQAN9MM5YQ10L0gbB3BUwDlq9kgEJ75gsgOuEg0E i6NiNiqVw7P1vEGSBSTYZKS2/plvVQotc5gI1tJo6DyDPooV1e1GcMC5YylIHDTdvItw h9oQ== X-Gm-Message-State: ABuFfogLjhyZlrVNYsFrqo7YW0rLtIxz3dQxcvaZ8xRh95VGdpBU8l2q Lrn2To1dtEB+s/RpkB5RWYZetm+gZLA= X-Google-Smtp-Source: ACcGV63PdAQZkJ4dIPXcS7cj0wTAz3eufoUzlrTIEIvrYHUVB8vqOM8uhXdFFqOtzL2LiUi0U6H3Tw== X-Received: by 2002:a63:7f0e:: with SMTP id a14-v6mr1788747pgd.296.1538579606798; Wed, 03 Oct 2018 08:13:26 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id t26-v6sm3140106pfa.158.2018.10.03.08.13.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 08:13:25 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:43 +0700 Message-Id: <1538579266-8389-10-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v1 09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: "Edgar E. Iglesias" When QEMU provides the equivalent of the EL3 firmware, we need to enable HVCs in scr_el3 when turning on CPUs that target EL2. Signed-off-by: Edgar E. Iglesias Reviewed-by: Peter Maydell --- target/arm/arm-powerctl.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index ce55eeb..54f2974 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, struct CpuOnInfo *info = (struct CpuOnInfo *) data.host_ptr; /* Initialize the cpu we are turning on */ + qemu_log("CPU%d reset\n", target_cpu_state->cpu_index); cpu_reset(target_cpu_state); target_cpu_state->halted = 0; @@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; + + /* + * If QEMU is providing the equivalent of EL3 firmware, then we need + * to make sure a CPU targeting EL2 comes out of reset with a + * functional HVC insn. + */ + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) + && info->target_el == 2) { + target_cpu->env.cp15.scr_el3 |= SCR_HCE; + } } /* We check if the started CPU is now at the correct level */