| Message ID | 1538579266-8389-5-git-send-email-edgar.iglesias@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm: Add first models of Xilinx Versal SoC | expand |
On 10/03/2018 08:07 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add macro with max number of DMA descriptor words. > No functional change. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/net/cadence_gem.c | 4 ++-- > include/hw/net/cadence_gem.h | 5 ++++- > 2 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c > index 31f3fe0..4d769b0 100644 > --- a/hw/net/cadence_gem.c > +++ b/hw/net/cadence_gem.c > @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, > */ > static void gem_transmit(CadenceGEMState *s) > { > - uint32_t desc[2]; > + uint32_t desc[DESC_MAX_NUM_WORDS]; > hwaddr packet_desc_addr; > uint8_t tx_packet[2048]; > uint8_t *p; > @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) > > /* Last descriptor for this packet; hand the whole thing off */ > if (tx_desc_get_last(desc)) { > - uint32_t desc_first[2]; > + uint32_t desc_first[DESC_MAX_NUM_WORDS]; > > /* Modify the 1st descriptor of this packet to be owned by > * the processor. > diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h > index 633d564..b33ef65 100644 > --- a/include/hw/net/cadence_gem.h > +++ b/include/hw/net/cadence_gem.h > @@ -32,6 +32,9 @@ > > #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ > > +/* Max number of words in a DMA descriptor. */ > +#define DESC_MAX_NUM_WORDS 2 > + > #define MAX_PRIORITY_QUEUES 8 > #define MAX_TYPE1_SCREENERS 16 > #define MAX_TYPE2_SCREENERS 16 > @@ -74,7 +77,7 @@ typedef struct CadenceGEMState { > > uint8_t can_rx_state; /* Debug only */ > > - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; > + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; > > bool sar_active[4]; > } CadenceGEMState; >
On 03/10/2018 17:07, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add macro with max number of DMA descriptor words. > No functional change. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > hw/net/cadence_gem.c | 4 ++-- > include/hw/net/cadence_gem.h | 5 ++++- > 2 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c > index 31f3fe0..4d769b0 100644 > --- a/hw/net/cadence_gem.c > +++ b/hw/net/cadence_gem.c > @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, > */ > static void gem_transmit(CadenceGEMState *s) > { > - uint32_t desc[2]; > + uint32_t desc[DESC_MAX_NUM_WORDS]; > hwaddr packet_desc_addr; > uint8_t tx_packet[2048]; > uint8_t *p; > @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) > > /* Last descriptor for this packet; hand the whole thing off */ > if (tx_desc_get_last(desc)) { > - uint32_t desc_first[2]; > + uint32_t desc_first[DESC_MAX_NUM_WORDS]; > > /* Modify the 1st descriptor of this packet to be owned by > * the processor. > diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h > index 633d564..b33ef65 100644 > --- a/include/hw/net/cadence_gem.h > +++ b/include/hw/net/cadence_gem.h > @@ -32,6 +32,9 @@ > > #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ > > +/* Max number of words in a DMA descriptor. */ > +#define DESC_MAX_NUM_WORDS 2 > + > #define MAX_PRIORITY_QUEUES 8 > #define MAX_TYPE1_SCREENERS 16 > #define MAX_TYPE2_SCREENERS 16 > @@ -74,7 +77,7 @@ typedef struct CadenceGEMState { > > uint8_t can_rx_state; /* Debug only */ > > - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; > + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; > > bool sar_active[4]; > } CadenceGEMState; >
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 31f3fe0..4d769b0 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, */ static void gem_transmit(CadenceGEMState *s) { - uint32_t desc[2]; + uint32_t desc[DESC_MAX_NUM_WORDS]; hwaddr packet_desc_addr; uint8_t tx_packet[2048]; uint8_t *p; @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { - uint32_t desc_first[2]; + uint32_t desc_first[DESC_MAX_NUM_WORDS]; /* Modify the 1st descriptor of this packet to be owned by * the processor. diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 633d564..b33ef65 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -32,6 +32,9 @@ #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ +/* Max number of words in a DMA descriptor. */ +#define DESC_MAX_NUM_WORDS 2 + #define MAX_PRIORITY_QUEUES 8 #define MAX_TYPE1_SCREENERS 16 #define MAX_TYPE2_SCREENERS 16 @@ -74,7 +77,7 @@ typedef struct CadenceGEMState { uint8_t can_rx_state; /* Debug only */ - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; bool sar_active[4]; } CadenceGEMState;