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[80.66.210.96]) by smtp.gmail.com with ESMTPSA id y19sm5478737wmj.2.2018.11.14.02.56.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 02:56:53 -0800 (PST) From: Dario Faggioli To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2018 11:57:09 +0100 Message-ID: <154219302946.19470.14979106134197499918.stgit@wayrath> In-Reply-To: <154219299016.19470.9372139354280787961.stgit@wayrath> References: <154219299016.19470.9372139354280787961.stgit@wayrath> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.65 Subject: [Qemu-devel] [RFC PATCH 3/3] i386: custom cache size in AMD's CPUID descriptors too X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP If specified on the command line, alter the cache size(s) properties accordingly, before encoding them in the AMD's CPUID cache descriptors too (i.e., 80000006 and 8000001d). Signed-off-by: Dario Faggioli --- Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost --- 0 files changed diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 17aff19561..4949d6b907 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4490,6 +4490,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (L2_DTLB_4K_ENTRIES << 16) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (L2_ITLB_4K_ENTRIES); + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l2_cache, + cpu->l2_cache_size); + if (cpu->enable_l3_cache && cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l3_cache, + cpu->l3_cache_size); encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, cpu->enable_l3_cache ? env->cache_info_amd.l3_cache : NULL, @@ -4546,10 +4552,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l2_cache, + cpu->l2_cache_size * MiB); encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ + if (cpu->enable_l3_cache && cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l3_cache, + cpu->l3_cache_size * MiB); encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, eax, ebx, ecx, edx); break;