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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id g12sm24897149pfd.72.2019.03.17.01.03.16 (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 17 Mar 2019 01:03:16 -0700 (PDT) From: Bin Meng To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Palmer Dabbelt , Bastian Koppelmann , Sagar Karandikar Date: Sun, 17 Mar 2019 01:03:10 -0700 Message-Id: <1552809791-7714-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP At present the sifive uart model only generates RX interrupt. This updates it to generate TX interrupt so that it is more useful. Note the TX fifo is still unimplemented. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_uart.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 456a3d3..3b3f94f 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -51,7 +51,8 @@ static uint64_t uart_ip(SiFiveUARTState *s) static void update_irq(SiFiveUARTState *s) { int cond = 0; - if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { + if ((s->ie & SIFIVE_UART_IE_TXWM) || + ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) { cond = 1; } if (cond) { @@ -108,6 +109,7 @@ uart_write(void *opaque, hwaddr addr, switch (addr) { case SIFIVE_UART_TXFIFO: qemu_chr_fe_write(&s->chr, &ch, 1); + update_irq(s); return; case SIFIVE_UART_IE: s->ie = val64;