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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.37 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:37 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:03 -0700 Message-Id: <1565163924-18621-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP It is not useful if we only have one management CPU. Signed-off-by: Bin Meng --- Changes in v2: - update the file header to indicate at least 2 harts are created hw/riscv/sifive_u.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 821f1d5..91f3c76 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,8 +10,8 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * - * This board currently generates devicetree dynamically that indicates at most - * five harts. + * This board currently generates devicetree dynamically that indicates at least + * two harts and up to five harts. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -429,6 +429,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) * management CPU. */ mc->max_cpus = 5; + /* It is not useful if we only have one management CPU */ + mc->min_cpus = 2; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)