diff mbox series

[v3,13/18] hw/i386: Introduce apicid_from_cpu_idx in PCMachineState

Message ID 157541990559.46157.14383447284580991446.stgit@naples-babu.amd.com (mailing list archive)
State New, archived
Headers show
Series APIC ID fixes for AMD EPYC CPU models | expand

Commit Message

Babu Moger Dec. 4, 2019, 12:38 a.m. UTC
Add function pointers in PCMachineState to handle apic id specific
functionalities. This will be used to initialize with correct handlers based on
the cpu model selected.

x86_apicid_from_cpu_idx will be default handler.

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 hw/i386/pc.c         |    5 ++++-
 include/hw/i386/pc.h |    5 +++++
 2 files changed, 9 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7f30104a6b..52aea4a652 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -894,7 +894,7 @@  static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
 
     initialize_topo_info(&topo_info, pcms, ms);
 
-    correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
+    correct_id = pcms->apicid_from_cpu_idx(&topo_info, cpu_index);
     if (pcmc->compat_apic_id_mode) {
         if (cpu_index != correct_id && !warned && !qtest_enabled()) {
             error_report("APIC IDs set in compatibility mode, "
@@ -2679,6 +2679,9 @@  static void pc_machine_initfn(Object *obj)
     pcms->pit_enabled = true;
     pcms->smp_dies = 1;
 
+    /* Initialize the apic id related handlers */
+    pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
+
     pc_system_flash_create(pcms);
 }
 
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 37bfd95113..56aa0e45b5 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -16,6 +16,7 @@ 
 #include "hw/mem/pc-dimm.h"
 #include "hw/mem/nvdimm.h"
 #include "hw/acpi/acpi_dev_interface.h"
+#include "hw/i386/topology.h"
 
 #define HPET_INTCAP "hpet-intcap"
 
@@ -67,6 +68,10 @@  struct PCMachineState {
     uint64_t numa_nodes;
     uint64_t *node_mem;
 
+    /* Apic id specific handlers */
+    uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
+                                    unsigned cpu_index);
+
     /* Address space used by IOAPIC device. All IOAPIC interrupts
      * will be translated to MSI messages in the address space. */
     AddressSpace *ioapic_as;