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Fri, 14 Feb 2020 05:21:10 -0800 Received: from xsj-pvapsmtp01 (mail.xilinx.com [149.199.38.66] (may be forged)) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01EDL97s013816; Fri, 14 Feb 2020 05:21:09 -0800 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j2au5-0006fq-DM; Fri, 14 Feb 2020 05:21:09 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id EB4CB13C0374; Fri, 14 Feb 2020 18:47:02 +0530 (IST) From: Sai Pavan Boddu To: "Edgar E . Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH 2/3] cpu/a9mpcore: Add num priority bits property Date: Fri, 14 Feb 2020 18:46:51 +0530 Message-Id: <1581686212-9625-3-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(136003)(346002)(376002)(39850400004)(189003)(199004)(478600001)(110136005)(2616005)(26005)(6266002)(186003)(4326008)(336012)(316002)(70206006)(70586007)(81166006)(81156014)(8676002)(42186006)(8936002)(36756003)(356004)(6666004)(5660300002)(2906002)(426003)(42866002); DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR02MB5549; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 22ea4f00-23ac-4881-a674-08d7b150c558 X-MS-TrafficTypeDiagnostic: SN6PR02MB5549: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:119; X-Forefront-PRVS: 03137AC81E X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VHPJDShSk0EN6pRR0KRrRp/l6pi1KEugsTvhsRSL9wsDmvL2KyAzLQ2o13RKpTB1iFIsPehx0mnVMgm/9/TFUs4ATgiLD/7X7Fro/pMCAfivNIXfSEhIgFTu+D/topFqnoQLkHupTbFcDGDvhZNO5jhgRjUt2D6m8abVWa20m7qRZis8mO6KC7UfDAoCSksGV78VGKnygQmNjUi6vg9ci3MF1KczBr3/E39h2oh0ZfsWHPT287UzaBhU9gNnFrH++33Ns9QMcCcKHqw9fIk3q7qxmLmvWhoqizYOzdHXzC5miaSF/OguiplhXOB2/X29toXkDnCQdkiKwVsHKHl40Lb2iBHSTz9wBrpqSEW7mnDBIwp/gLLwXI6kMbk4a1hCiHo94jUwjCvP1g/eOPsbXtjtHhd+CM8vQufPtMX4kZNZBNzB9p+72Vj7wgycuZ4Ti8yjnnh+rGrT8MTnLOa+YcCli/3Ps95qsUnSTsXvS9M= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2020 13:21:16.0894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22ea4f00-23ac-4881-a674-08d7b150c558 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5549 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.92.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Set number of priority bits property of gic as guided by machine configuration. Signed-off-by: Sai Pavan Boddu --- hw/cpu/a9mpcore.c | 2 ++ include/hw/cpu/a9mpcore.h | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 1f8bc8a..eb1e752 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -68,6 +68,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-prio-bits", s->n_prio_bits); /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. @@ -167,6 +168,7 @@ static Property a9mp_priv_properties[] = { * Other boards may differ and should set this property appropriately. */ DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + DEFINE_PROP_UINT32("num-priority-bits", A9MPPrivState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h index 5d67ca2..4f146bd 100644 --- a/include/hw/cpu/a9mpcore.h +++ b/include/hw/cpu/a9mpcore.h @@ -28,6 +28,7 @@ typedef struct A9MPPrivState { uint32_t num_cpu; MemoryRegion container; uint32_t num_irq; + uint32_t n_prio_bits; A9SCUState scu; GICState gic;