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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH v2 3/3] cpu/arm11mpcore: Set number of GIC priority bits to 4 Date: Fri, 21 Feb 2020 13:12:07 +0530 Message-Id: <1582270927-2568-4-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582270927-2568-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1582270927-2568-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(346002)(396003)(39860400002)(136003)(376002)(199004)(189003)(42186006)(426003)(316002)(70586007)(81156014)(81166006)(8676002)(70206006)(8936002)(336012)(110136005)(2616005)(6266002)(4744005)(186003)(26005)(4326008)(356004)(5660300002)(6666004)(2906002)(478600001)(36756003)(42866002); DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR02MB4334; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 32e7c70a-940d-47eb-c5e6-08d7b6a234cf X-MS-TrafficTypeDiagnostic: SN6PR02MB4334: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:78; X-Forefront-PRVS: 0320B28BE1 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: p89TLr+GNGTBsUx4T9zj74xaxKi4vRZEM2+dBD7imJhziBbkho0WZd+Je0hUWAHjYT3UcGrGXUCXa7Uq5c6nw8IIIfT8b5a8venGTxay59CG0iXIPMhvk/3jlFsOwnMBogJO//EpqeQM4UC2v5SCMATV/Mgb28WAtb6LCzWMtdGeUfXnKaCdI+JbPoZUkNLSc9Oce7+xSa81nzVfvHO5wqVwbHM5jgbKsjZTT/CMmbj9ZaFDgs2QKj325yMczzUt7I07wsXMHfl0kG6p/XlXoZIXRFkmJsxNVHW9PoJ8HYbfIWIaz1xVjNb9nh6eCTZ9MRkLSidH7/BrjPeQNtNPKXUlxk5/rg1y+Fvw308eOvJGCZTsLPcGW9oD3rcszskm9Uv/bRheN4UpetwuExgHLdKP1xSXkGes0tfH/4SrG8/4chHuEtUbwpBZHm9hdat4vLJBcE2OLNTpssTelPn1M8bqnLRMEwFpSkoRF39mIq+K87/0qozIdU2d4+JV4xbV X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2020 07:46:48.1912 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32e7c70a-940d-47eb-c5e6-08d7b6a234cf X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB4334 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.94.43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" ARM11MPCore GIC is implemented with 4 priority bits. Signed-off-by: Sai Pavan Boddu Suggested-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/cpu/arm11mpcore.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 2e3e87c..ab9fadb 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" +#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 static void mpcore_priv_set_irq(void *opaque, int irq, int level) { @@ -86,6 +87,10 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + ARM11MPCORE_NUM_GIC_PRIORITY_BITS); + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err);