@@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return ret;
}
+static uint32_t gic_fullprio_mask(GICState *s, int cpu)
+{
+ /*
+ * Return a mask word which clears the unimplemented priority
+ * bits from a priority value for an interrupt. (Not to be
+ * confused with the group priority, whose mask depends on BPR.)
+ */
+ int priBits;
+
+ if (gic_is_vcpu(cpu)) {
+ priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS;
+ } else {
+ priBits = s->n_prio_bits;
+ }
+ return ~0U << (8 - priBits);
+}
+
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs)
{
@@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
val = 0x80 | (val >> 1); /* Non-secure view */
}
+ val &= gic_fullprio_mask(s, cpu);
+
if (irq < GIC_INTERNAL) {
s->priority1[irq][cpu] = val;
} else {
@@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,
}
prio = (prio << 1) & 0xff; /* Non-secure view */
}
- return prio;
+ return prio & gic_fullprio_mask(s, cpu);
}
static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
@@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
return;
}
}
- s->priority_mask[cpu] = pmask;
+ s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu);
}
static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
@@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
+ if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS ||
+ (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) {
+ error_setg(errp, "num-priority-bits cannot be greater than %d"
+ " or less than %d", GIC_MAX_PRIORITY_BITS,
+ s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ GIC_MIN_PRIORITY_BITS);
+ return;
+ }
+
/* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
* enabled, virtualization extensions related interfaces (main virtual
* interface (s->vifaceiomem[0]) and virtual CPU interface).
@@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = {
DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
/* True if the GIC should implement the virtualization extensions */
DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
+ DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
DEFINE_PROP_END_OF_LIST(),
};
@@ -68,6 +68,8 @@
/* Number of SGI target-list bits */
#define GIC_TARGETLIST_BITS 8
+#define GIC_MAX_PRIORITY_BITS 8
+#define GIC_MIN_PRIORITY_BITS 4
#define TYPE_ARM_GIC "arm_gic"
#define ARM_GIC(obj) \
@@ -96,6 +96,7 @@ typedef struct GICState {
uint16_t priority_mask[GIC_NCPU_VCPU];
uint16_t running_priority[GIC_NCPU_VCPU];
uint16_t current_pending[GIC_NCPU_VCPU];
+ uint32_t n_prio_bits;
/* If we present the GICv2 without security extensions to a guest,
* the guest can configure the GICC_CTLR to configure group 1 binary point
Priority bits implemented in arm-gic can be 8 to 4, un-implemented bits are read as zeros(RAZ). Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> --- hw/intc/arm_gic.c | 33 +++++++++++++++++++++++++++++++-- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic.h | 2 ++ include/hw/intc/arm_gic_common.h | 1 + 4 files changed, 35 insertions(+), 2 deletions(-)