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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH v3 3/3] cpu/arm11mpcore: Set number of GIC priority bits to 4 Date: Mon, 24 Feb 2020 15:09:24 +0530 Message-Id: <1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(346002)(136003)(376002)(39860400002)(199004)(189003)(316002)(110136005)(6266002)(8936002)(81156014)(42186006)(2906002)(426003)(36756003)(8676002)(2616005)(336012)(81166006)(478600001)(6666004)(356004)(5660300002)(26005)(70586007)(4326008)(70206006)(186003); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR02MB5941; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: eccd0ca0-ea91-4f31-448e-08d7b90e1e4c X-MS-TrafficTypeDiagnostic: BYAPR02MB5941: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:78; X-Forefront-PRVS: 032334F434 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: itcAr0mLWVWDDCi/jJeIC99gnJppkAhIsKtOXFGX5Q7OxznIAbFd626oc49Ml86WC8q6DOx2dBax6Xb6UcXwR8zNQAALP2tm7oiLpDF8x+7x5Y7daSHxf0ZHZ16p406XYo7FjDkELWVYrDcCJik3aVGI1lT/5cYPCrJrN0dApJhZeQD6mUo+VRJcz9Qtj7LZSesaQvgvmtwCwNki1PTWMYVpT/vuIo6LoQa0iePKZ4vrLg6fbywT/VpqailLjahxATXK6DkWAnrUbQiRIAXX4o/stljpJvCU1JYblgjTkiyvZSn+KOTvel+TGt8Gmpn7f/SDmcjLuYKCVmLmQW1pJ1XhJYuWFSblc9v+a4z7dWz99eqi7jHz78eTJrdaGLu/pSjIJZ+kDgPVjGpMlyiuqECWTgxKz65EmqU5CnrTgGRndPoykkfTXeT3ji6XALCg X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2020 09:44:18.3928 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eccd0ca0-ea91-4f31-448e-08d7b90e1e4c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5941 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.244.73 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" ARM11MPCore GIC is implemented with 4 priority bits. Signed-off-by: Sai Pavan Boddu Suggested-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/cpu/arm11mpcore.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 2e3e87c..ab9fadb 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" +#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 static void mpcore_priv_set_irq(void *opaque, int irq, int level) { @@ -86,6 +87,10 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + ARM11MPCORE_NUM_GIC_PRIORITY_BITS); + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err);