From patchwork Sun Apr 5 04:45:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sundeep subbaraya X-Patchwork-Id: 11474567 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10B1181 for ; Sun, 5 Apr 2020 04:48:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA3C3206F5 for ; Sun, 5 Apr 2020 04:48:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ghmcgk9m" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DA3C3206F5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:44522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jKxD3-0006ad-2o for patchwork-qemu-devel@patchwork.kernel.org; Sun, 05 Apr 2020 00:48:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39714) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jKxAM-000446-0k for qemu-devel@nongnu.org; Sun, 05 Apr 2020 00:45:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jKxAK-00009s-Sa for qemu-devel@nongnu.org; Sun, 05 Apr 2020 00:45:49 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:38016) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jKxAK-00009Y-Mo; Sun, 05 Apr 2020 00:45:48 -0400 Received: by mail-pj1-x1043.google.com with SMTP id m15so4961286pje.3; Sat, 04 Apr 2020 21:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mnUjiO3eFVb5IikUPCFhl5zRRKuczfWeD8BaNcdN8Sw=; b=Ghmcgk9mQDPBW/T526f8yJ12BAJbokWGcsYuG7uzUoIdxGkzjj5l6DzP4qahAT//GX YsewuxMs/newdBRlhpzjN4JIWfQc4HDUdug/uJoGnKq7B4ZUtWroeI83+AdrP07mVd2p 0TgJ5ssmsr50IqGJsplTg1Uo+ha0dRcadujMzhvWYWG+433RPHlwTLjMDejouhiBeViS D6AfNUVr6eA+3IWcrje5k+v9wNqNgDSbRc8lxWJgYKmtyQMj6vIizJZY29zwqGoZUKw2 Bu2XAlSHlXWZex7c53/C+SreexIL3h6TTmCesRfhCk2uIprOXG3sVQA4YTK/NxGaXEEn QN0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mnUjiO3eFVb5IikUPCFhl5zRRKuczfWeD8BaNcdN8Sw=; b=C9GKhdLMCA54wK85xoz+mMrkujFIO2B3vEw/mLMlcY9FTcE/IiGXirvuedMez47XFD nQl625JaCsbVlqOhtrOZEoQnAxQqWFAaIP6SEQgISf0n7snOPwk8TDeP1XY/YxbxEI5o P319ZOWBRal2seMYFetE8X0bfJv10KtYlfazkQFwQGun/UXL8OBJ34Ke15MsFekPXkC4 qBShsy46jlAvUibFg2KsTznhH1SU/ZnrYo+ATA84zsYHStOjvpkPHuoXoxRbx6ZDRxcF gPP0zUUoiLolLvjlh9B0AeY1qbN7F0OFZKa28ZGnBAbBu0XxZ3efpzGiwB17ktrukNtm ZmlA== X-Gm-Message-State: AGi0Puan4twHiAAmW6BWBw2opAkX7jcJYwwtQW/Vt3YML8prNLTQ9qYI PN9G00aHW7gOHwM+cwvjP/z61fK6 X-Google-Smtp-Source: APiQypLsUgWAetkj04DTbkz75/+IHr6qHyQb7qfcmTEk2MZSeZ4zbx43bcJAZilO8tLvEFOPkSfpEA== X-Received: by 2002:a17:902:9a45:: with SMTP id x5mr13904313plv.296.1586061947801; Sat, 04 Apr 2020 21:45:47 -0700 (PDT) Received: from hyd1358.marvell.com ([115.113.156.2]) by smtp.googlemail.com with ESMTPSA id x25sm8164778pgc.63.2020.04.04.21.45.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 04 Apr 2020 21:45:47 -0700 (PDT) From: sundeep.lkml@gmail.com To: jasowang@redhat.com, peter.maydell@linaro.org, philmd@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [Qemu-devel PATCH 2/2] msf2: Add EMAC block to SmartFusion2 SoC Date: Sun, 5 Apr 2020 10:15:31 +0530 Message-Id: <1586061931-12600-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586061931-12600-1-git-send-email-sundeep.lkml@gmail.com> References: <1586061931-12600-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Subbaraya Sundeep Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Subbaraya Sundeep With SmartFusion2 Ethernet MAC model in place this patch adds the same to SoC. Signed-off-by: Subbaraya Sundeep --- hw/arm/msf2-soc.c | 21 ++++++++++++++++++++- include/hw/arm/msf2-soc.h | 3 +++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 588d643..2f2db6d 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -35,6 +35,7 @@ #define MSF2_TIMER_BASE 0x40004000 #define MSF2_SYSREG_BASE 0x40038000 +#define MSF2_EMAC_BASE 0x40041000 #define ENVM_BASE_ADDRESS 0x60000000 @@ -55,6 +56,7 @@ static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; +static const int emac_irq[MSF2_NUM_EMACS] = { 12 }; static void do_sys_reset(void *opaque, int n, int level) { @@ -81,6 +83,13 @@ static void m2sxxx_soc_initfn(Object *obj) sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), TYPE_MSS_SPI); } + + sysbus_init_child_obj(obj, "eth", &s->emac, sizeof(s->emac), + TYPE_MSS_EMAC); + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC); + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); + } } static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -192,6 +201,17 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) g_free(bus_name); } + dev = DEVICE(&s->emac); + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, emac_irq[0])); + /* Below devices are not modelled yet. */ create_unimplemented_device("i2c_0", 0x40002000, 0x1000); create_unimplemented_device("dma", 0x40003000, 0x1000); @@ -202,7 +222,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("can", 0x40015000, 0x1000); create_unimplemented_device("rtc", 0x40017000, 0x1000); create_unimplemented_device("apb_config", 0x40020000, 0x10000); - create_unimplemented_device("emac", 0x40041000, 0x1000); create_unimplemented_device("usb", 0x40043000, 0x1000); } diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 3cfe5c7..296ed03 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -29,12 +29,14 @@ #include "hw/timer/mss-timer.h" #include "hw/misc/msf2-sysreg.h" #include "hw/ssi/mss-spi.h" +#include "hw/net/msf2-emac.h" #define TYPE_MSF2_SOC "msf2-soc" #define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) #define MSF2_NUM_SPIS 2 #define MSF2_NUM_UARTS 2 +#define MSF2_NUM_EMACS 1 /* * System timer consists of two programmable 32-bit @@ -62,6 +64,7 @@ typedef struct MSF2State { MSF2SysregState sysreg; MSSTimerState timer; MSSSpiState spi[MSF2_NUM_SPIS]; + MSF2EmacState emac; } MSF2State; #endif