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[34.92.144.28]) by smtp.gmail.com with ESMTPSA id a12sm6173654pfr.28.2020.05.03.03.24.31 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 May 2020 03:24:33 -0700 (PDT) From: Huacai Chen X-Google-Original-From: Huacai Chen To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic Subject: [PATCH for-5.1 V3 3/7] hw/mips: Add CPU IRQ3 delivery for KVM Date: Sun, 3 May 2020 18:20:17 +0800 Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1588501221-1205-1-git-send-email-chenhc@lemote.com> References: <1588501221-1205-1-git-send-email-chenhc@lemote.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=zltjiangshi@gmail.com; helo=mail-pf1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Huacai Chen , Aleksandar Rikalo , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add IP3 delivery as well, because Loongson-3 based machine use both IRQ2 (CPU's IP2) and IRQ3 (CPU's IP3). Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang Reviewed-by: Aleksandar Markovic --- hw/mips/mips_int.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 796730b..982ce34 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -48,14 +48,14 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) if (level) { env->CP0_Cause |= 1 << (irq + CP0Ca_IP); - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) { kvm_mips_set_interrupt(cpu, irq, level); } } else { env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) { kvm_mips_set_interrupt(cpu, irq, level); } }