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Sat, 29 Aug 2020 00:49:47 +0530 (IST) From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?utf-8?q?=27Marc-Andr=C3=A9_Lureau?= =?utf-8?q?=27?= , Paolo Bonzini , Gerd Hoffmann , "Edgar E . Iglesias" , Francisco Iglesias Subject: [PATCH v4 7/7] Versal: Connect DWC3 controller with virt-versal Date: Sat, 29 Aug 2020 00:49:40 +0530 Message-Id: <1598642380-27817-8-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598642380-27817-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1598642380-27817-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: d13649e8-2d19-418f-9de4-08d84b86b26b X-MS-TrafficTypeDiagnostic: CH2PR02MB6024: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:119; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OUy05BFJq8KMzkmmc3S6q44M0R2wo9++T8QVCmeQA6eY6FRI1TYsPXfW2d3cxXKtRrhFHuITYzceBYe5EN3KN4RnjVqS9ezYaqgQ7j4YvgG9tfesqnljdVj4b92JvRT35h7Qjnfn1XtD7wyyQK84VP2MtXXhLxdf1lI5qOmwEkABOKuszEpUhPaufRfhML2X9IDhVog8Z/E7Ww6Spzxx1OCwHCk6EBacnOAkuMyyA1rGcD6h0PNJtFvowlk81Oi32BYUsca3DtqVx5OVd089Kf7eh6SSeYyRx7iVOJbX43FrywYTfEl5qWiXeJZmI+myR/0dItmVfsEkeKelhObI8W3ewXxy3OVHzZsw6YwGC7oQTz82jrv1ScVw7aKCCU3hzfBCuZVNJMICm7tKBKwbZQ== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(39860400002)(396003)(376002)(346002)(136003)(46966005)(83380400001)(356005)(26005)(47076004)(6666004)(6636002)(2906002)(70206006)(81166007)(70586007)(426003)(2616005)(82310400002)(186003)(82740400003)(336012)(54906003)(7416002)(6266002)(8676002)(4326008)(8936002)(5660300002)(316002)(110136005)(36756003)(478600001)(42186006); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2020 19:15:16.3883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d13649e8-2d19-418f-9de4-08d84b86b26b X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT039.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6024 Received-SPF: pass client-ip=40.107.220.74; envelope-from=saipava@xilinx.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/28 15:15:18 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Vikram Garhwal , sai.pavan.boddu@xilinx.com, qemu-devel@nongnu.org, Paul Zimmerman , Alistair Francis , Ying Fang , =?utf-8?q?=27Philippe_Mathieu-Daud=C3=A9?= =?utf-8?q?=27?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Vikram Garhwal Connect dwc3 controller and usb2-reg module to virt-versal. Configure it as dual port host controller. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu --- hw/arm/xlnx-versal-virt.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ hw/arm/xlnx-versal.c | 38 ++++++++++++++++++++++++++++ include/hw/arm/xlnx-versal.h | 14 +++++++++++ 3 files changed, 111 insertions(+) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 4b3152e..398693d 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -39,6 +39,8 @@ typedef struct VersalVirt { uint32_t ethernet_phy[2]; uint32_t clk_125Mhz; uint32_t clk_25Mhz; + uint32_t usb; + uint32_t dwc; } phandle; struct arm_boot_info binfo; @@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s) s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); + s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); + s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); /* Create /chosen node for load_dtb. */ qemu_fdt_add_subnode(s->fdt, "/chosen"); @@ -148,6 +152,60 @@ static void fdt_add_timer_nodes(VersalVirt *s) compat, sizeof(compat)); } +static void fdt_add_usb_xhci_nodes(VersalVirt *s) +{ + const char clocknames[] = "bus_clk\0ref_clk"; + char *usb2name = g_strdup_printf("/usb@ff9d0000"); + const char dwcCompat[] = "xlnx,versal-dwc3"; + qemu_fdt_add_subnode(s->fdt, usb2name); + qemu_fdt_setprop(s->fdt, usb2name, "compatible", + dwcCompat, sizeof(dwcCompat)); + qemu_fdt_setprop_sized_cells(s->fdt, usb2name, "reg", + 2, MM_USB2_REGS, 2, 0x100); + qemu_fdt_setprop(s->fdt, usb2name, "clock-names", + clocknames, sizeof(clocknames)); + qemu_fdt_setprop_cells(s->fdt, usb2name, "clocks", + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); + qemu_fdt_setprop(s->fdt, usb2name, "ranges", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, usb2name, "#address-cells", 2); + qemu_fdt_setprop_cell(s->fdt, usb2name, "#size-cells", 2); + qemu_fdt_setprop_cell(s->fdt, usb2name, "phandle", s->phandle.usb); + g_free(usb2name); + + { + uint64_t addr = MM_USB_XHCI_0; + unsigned int irq = VERSAL_USB0_IRQ_0; + const char compat[] = "snps,dwc3"; + const char intName[] = "dwc_usb3"; + uint32_t frameLen = 0x20; + + char *name = g_strdup_printf("/usb@ff9d0000/dwc3@%" PRIx64, addr); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, addr, 2, MM_USB_XHCI_SIZE_0); + qemu_fdt_setprop(s->fdt, name, "interrupt-names", + intName, sizeof(intName)); + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(s->fdt, name, + "snps,quirk-frame-length-adjustment", + frameLen); + qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); + qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); + qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,usb3_lpm_capable", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); + qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); + g_free(name); + } +} static void fdt_add_uart_nodes(VersalVirt *s) { uint64_t addrs[] = { MM_UART1, MM_UART0 }; @@ -515,6 +573,7 @@ static void versal_virt_init(MachineState *machine) fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); fdt_add_zdma_nodes(s); + fdt_add_usb_xhci_nodes(s); fdt_add_sd_nodes(s); fdt_add_rtc_node(s); fdt_add_cpu_nodes(s, psci_conduit); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index e3aa4bd..5cb03a1 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -145,6 +145,43 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic) } } +static void versal_create_usbs(Versal *s, qemu_irq *pic) +{ + char *name = g_strdup_printf("dwc3-0"); + DeviceState *dev, *xhci_dev; + MemoryRegion *mr; + + object_initialize_child(OBJECT(s), name, &s->fpd.iou.dwc3, + TYPE_USB_DWC3); + dev = DEVICE(&s->fpd.iou.dwc3); + xhci_dev = DEVICE(&s->fpd.iou.dwc3.sysbus_xhci); + + object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps), + &error_abort); + qdev_prop_set_uint32(xhci_dev, "intrs", 4); + qdev_prop_set_uint32(xhci_dev, "slots", 2); + + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0 + 0xC100 , mr); + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr); + + sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0, pic[VERSAL_USB0_IRQ_0]); + g_free(name); + + name = g_strdup_printf("usb2reg-0"); + object_initialize_child(OBJECT(s), name, &s->fpd.iou.Usb2Regs, + "xlnx.usb2_regs"); + dev = DEVICE(&s->fpd.iou.Usb2Regs); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB2_REGS, mr); + g_free(name); +} + static void versal_create_gems(Versal *s, qemu_irq *pic) { int i; @@ -332,6 +369,7 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); versal_create_uarts(s, pic); + versal_create_usbs(s, pic); versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_sds(s, pic); diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 9c9f47b..e19cfd5 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -20,6 +20,8 @@ #include "hw/dma/xlnx-zdma.h" #include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" +#include "hw/usb/hcd-dwc3.h" +#include "hw/misc/xlnx-versal-usb2-regs.h" #define TYPE_XLNX_VERSAL "xlnx-versal" #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) @@ -42,6 +44,11 @@ typedef struct Versal { ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; GICv3State gic; } apu; + + struct { + USBDWC3 dwc3; + XlnxUsb2Regs Usb2Regs; + } iou; } fpd; MemoryRegion mr_ps; @@ -87,6 +94,7 @@ typedef struct Versal { #define VERSAL_UART0_IRQ_0 18 #define VERSAL_UART1_IRQ_0 19 +#define VERSAL_USB0_IRQ_0 22 #define VERSAL_GEM0_IRQ_0 56 #define VERSAL_GEM0_WAKE_IRQ_0 57 #define VERSAL_GEM1_IRQ_0 58 @@ -124,6 +132,12 @@ typedef struct Versal { #define MM_OCM 0xfffc0000U #define MM_OCM_SIZE 0x40000 +#define MM_USB2_REGS 0xFF9D0000 +#define MM_USB2_SIZE 0x10000 + +#define MM_USB_XHCI_0 0xFE200000 +#define MM_USB_XHCI_SIZE_0 0x10000 + #define MM_TOP_DDR 0x0 #define MM_TOP_DDR_SIZE 0x80000000U #define MM_TOP_DDR_2 0x800000000ULL