| Message ID | 1606811915-8492-5-git-send-email-sai.pavan.boddu@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Versal usb model | expand |
On Tue, 1 Dec 2020 at 08:34, Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> wrote: > > From: Vikram Garhwal <fnu.vikram@xilinx.com> > > Connect VersalUbs2 subsystem to xlnx-versal SOC, its placed Typo : "VersalUSB2". > in iou of lpd domain and configure it as dual port host controller. > Add the respective guest dts nodes for "xlnx-versal-virt" machine. > > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Code looks OK but I'll let somebody else from Xilinx review the detail. > +static void fdt_add_usb_xhci_nodes(VersalVirt *s) > +{ > + const char clocknames[] = "bus_clk\0ref_clk"; > + char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); > + const char compat[] = "xlnx,versal-dwc3"; > + > + qemu_fdt_add_subnode(s->fdt, name); > + qemu_fdt_setprop(s->fdt, name, "compatible", > + compat, sizeof(compat)); > + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", > + 2, MM_USB2_CTRL_REGS, > + 2, MM_USB2_CTRL_REGS_SIZE); > + qemu_fdt_setprop(s->fdt, name, "clock-names", > + clocknames, sizeof(clocknames)); > + qemu_fdt_setprop_cells(s->fdt, name, "clocks", > + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); > + qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); > + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); > + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); > + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); > + g_free(name); > + > + { > + const char irq_name[] = "dwc_usb3"; > + const char compat[] = "snps,dwc3"; Minor coding style side note, but I'm not hugely fond of code blocks in the middle of functions just for declaring variables. You could either put these variable declarations at the top of the function, or if you think the code in the block is self contained and worth putting in its own function you could do that. thanks -- PMM
On Tue, Dec 01, 2020 at 11:34:25AM +0000, Peter Maydell wrote: > On Tue, 1 Dec 2020 at 08:34, Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> wrote: > > > > From: Vikram Garhwal <fnu.vikram@xilinx.com> > > > > Connect VersalUbs2 subsystem to xlnx-versal SOC, its placed > > Typo : "VersalUSB2". > > > > in iou of lpd domain and configure it as dual port host controller. > > Add the respective guest dts nodes for "xlnx-versal-virt" machine. > > > > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> > > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> > > Code looks OK but I'll let somebody else from Xilinx review the detail. > > > +static void fdt_add_usb_xhci_nodes(VersalVirt *s) > > +{ > > + const char clocknames[] = "bus_clk\0ref_clk"; > > + char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); > > + const char compat[] = "xlnx,versal-dwc3"; > > + > > + qemu_fdt_add_subnode(s->fdt, name); > > + qemu_fdt_setprop(s->fdt, name, "compatible", > > + compat, sizeof(compat)); > > + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", > > + 2, MM_USB2_CTRL_REGS, > > + 2, MM_USB2_CTRL_REGS_SIZE); > > + qemu_fdt_setprop(s->fdt, name, "clock-names", > > + clocknames, sizeof(clocknames)); > > + qemu_fdt_setprop_cells(s->fdt, name, "clocks", > > + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); > > + qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); > > + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); > > + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); > > + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); > > + g_free(name); > > + > > + { > > + const char irq_name[] = "dwc_usb3"; > > + const char compat[] = "snps,dwc3"; > > Minor coding style side note, but I'm not hugely fond of > code blocks in the middle of functions just for declaring > variables. You could either put these variable declarations > at the top of the function, or if you think the code in the > block is self contained and worth putting in its own function > you could do that. > Hi Sai, I beleive I had already reviewed a previous version of this patch so after you fix the stuff the Peter pointed out feel free to add my Rb: Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Cheers, Edgar
Hi Peter/Edgar, > -----Original Message----- > From: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > Sent: Thursday, December 3, 2020 11:35 PM > To: Peter Maydell <peter.maydell@linaro.org> > Cc: Sai Pavan Boddu <saipava@xilinx.com>; Markus Armbruster > <armbru@redhat.com>; Marc-André Lureau <marcandre.lureau@redhat.com>; > Paolo Bonzini <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; > Edgar Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias > <figlesia@xilinx.com>; Alistair Francis <alistair.francis@wdc.com>; Eduardo > Habkost <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>; > Philippe Mathieu-Daudé <philmd@redhat.com>; Vikram Garhwal > <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>; Sai Pavan Boddu > <saipava@xilinx.com>; QEMU Developers <qemu-devel@nongnu.org> > Subject: Re: [PATCH v14 4/4] arm: xlnx-versal: Connect usb to virt-versal > > On Tue, Dec 01, 2020 at 11:34:25AM +0000, Peter Maydell wrote: > > On Tue, 1 Dec 2020 at 08:34, Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> > wrote: > > > > > > From: Vikram Garhwal <fnu.vikram@xilinx.com> > > > > > > Connect VersalUbs2 subsystem to xlnx-versal SOC, its placed > > > > Typo : "VersalUSB2". > > > > > > > in iou of lpd domain and configure it as dual port host controller. > > > Add the respective guest dts nodes for "xlnx-versal-virt" machine. > > > > > > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> > > > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> > > > > Code looks OK but I'll let somebody else from Xilinx review the detail. > > > > > +static void fdt_add_usb_xhci_nodes(VersalVirt *s) { > > > + const char clocknames[] = "bus_clk\0ref_clk"; > > > + char *name = g_strdup_printf("/usb@%" PRIx32, > MM_USB2_CTRL_REGS); > > > + const char compat[] = "xlnx,versal-dwc3"; > > > + > > > + qemu_fdt_add_subnode(s->fdt, name); > > > + qemu_fdt_setprop(s->fdt, name, "compatible", > > > + compat, sizeof(compat)); > > > + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", > > > + 2, MM_USB2_CTRL_REGS, > > > + 2, MM_USB2_CTRL_REGS_SIZE); > > > + qemu_fdt_setprop(s->fdt, name, "clock-names", > > > + clocknames, sizeof(clocknames)); > > > + qemu_fdt_setprop_cells(s->fdt, name, "clocks", > > > + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); > > > + qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); > > > + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); > > > + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); > > > + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); > > > + g_free(name); > > > + > > > + { > > > + const char irq_name[] = "dwc_usb3"; > > > + const char compat[] = "snps,dwc3"; > > > > Minor coding style side note, but I'm not hugely fond of code blocks > > in the middle of functions just for declaring variables. You could > > either put these variable declarations at the top of the function, or > > if you think the code in the block is self contained and worth putting > > in its own function you could do that. [Sai Pavan Boddu] Yeah. I could fix this in V15, Thanks. > > > > Hi Sai, I beleive I had already reviewed a previous version of this patch so after > you fix the stuff the Peter pointed out feel free to add my > Rb: > > Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [Sai Pavan Boddu] Thanks Edgar. Regards, Sai Pavan > > Cheers, > Edgar
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index ee12822..84b450e 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -39,6 +39,8 @@ struct VersalVirt { uint32_t ethernet_phy[2]; uint32_t clk_125Mhz; uint32_t clk_25Mhz; + uint32_t usb; + uint32_t dwc; } phandle; struct arm_boot_info binfo; @@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s) s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); + s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); + s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); /* Create /chosen node for load_dtb. */ qemu_fdt_add_subnode(s->fdt, "/chosen"); @@ -148,6 +152,59 @@ static void fdt_add_timer_nodes(VersalVirt *s) compat, sizeof(compat)); } +static void fdt_add_usb_xhci_nodes(VersalVirt *s) +{ + const char clocknames[] = "bus_clk\0ref_clk"; + char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); + const char compat[] = "xlnx,versal-dwc3"; + + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB2_CTRL_REGS, + 2, MM_USB2_CTRL_REGS_SIZE); + qemu_fdt_setprop(s->fdt, name, "clock-names", + clocknames, sizeof(clocknames)); + qemu_fdt_setprop_cells(s->fdt, name, "clocks", + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); + qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); + g_free(name); + + { + const char irq_name[] = "dwc_usb3"; + const char compat[] = "snps,dwc3"; + + name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, + MM_USB2_CTRL_REGS, MM_USB_0); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB_0, 2, MM_USB_0_SIZE); + qemu_fdt_setprop(s->fdt, name, "interrupt-names", + irq_name, sizeof(irq_name)); + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(s->fdt, name, + "snps,quirk-frame-length-adjustment", 0x20); + qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); + qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); + qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); + qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); + g_free(name); + } +} + static void fdt_add_uart_nodes(VersalVirt *s) { uint64_t addrs[] = { MM_UART1, MM_UART0 }; @@ -515,6 +572,7 @@ static void versal_virt_init(MachineState *machine) fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); fdt_add_zdma_nodes(s); + fdt_add_usb_xhci_nodes(s); fdt_add_sd_nodes(s); fdt_add_rtc_node(s); fdt_add_cpu_nodes(s, psci_conduit); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 12ba6c4..b077716 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -145,6 +145,31 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic) } } +static void versal_create_usbs(Versal *s, qemu_irq *pic) +{ + DeviceState *dev; + MemoryRegion *mr; + + object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, + TYPE_XILINX_VERSAL_USB2); + dev = DEVICE(&s->lpd.iou.usb); + + object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), + &error_abort); + qdev_prop_set_uint32(dev, "intrs", 1); + qdev_prop_set_uint32(dev, "slots", 2); + + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); +} + static void versal_create_gems(Versal *s, qemu_irq *pic) { int i; @@ -333,6 +358,7 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); versal_create_uarts(s, pic); + versal_create_usbs(s, pic); versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_sds(s, pic); diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 8ce8e63..2b76885 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -21,6 +21,7 @@ #include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" +#include "hw/usb/xlnx-usb-subsystem.h" #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -59,6 +60,7 @@ struct Versal { PL011State uart[XLNX_VERSAL_NR_UARTS]; CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; + VersalUsb2 usb; } iou; } lpd; @@ -88,6 +90,7 @@ struct Versal { #define VERSAL_UART0_IRQ_0 18 #define VERSAL_UART1_IRQ_0 19 +#define VERSAL_USB0_IRQ_0 22 #define VERSAL_GEM0_IRQ_0 56 #define VERSAL_GEM0_WAKE_IRQ_0 57 #define VERSAL_GEM1_IRQ_0 58 @@ -125,6 +128,12 @@ struct Versal { #define MM_OCM 0xfffc0000U #define MM_OCM_SIZE 0x40000 +#define MM_USB2_CTRL_REGS 0xFF9D0000 +#define MM_USB2_CTRL_REGS_SIZE 0x10000 + +#define MM_USB_0 0xFE200000 +#define MM_USB_0_SIZE 0x10000 + #define MM_TOP_DDR 0x0 #define MM_TOP_DDR_SIZE 0x80000000U #define MM_TOP_DDR_2 0x800000000ULL