@@ -73,6 +73,8 @@
&fmt_fdcj fd cj
&fmt_cdrj cd rj
&fmt_rdcj rd cj
+&fmt_fdrjrk fd rj rk
+&fmt_fdrjsi12 fd rj si12
#
# Formats
@@ -108,6 +110,8 @@
@fmt_fdcj .... ........ ..... ..... .. ... ..... &fmt_fdcj %fd %cj
@fmt_cdrj .... ........ ..... ..... ..... .. ... &fmt_cdrj %cd %rj
@fmt_rdcj .... ........ ..... ..... .. ... ..... &fmt_rdcj %rd %cj
+@fmt_fdrjrk .... ........ ..... ..... ..... ..... &fmt_fdrjrk %fd %rj %rk
+@fmt_fdrjsi12 .... ...... ............ ..... ..... &fmt_fdrjsi12 %fd %rj %si12
#
# Fixed point arithmetic operation instruction
@@ -427,3 +431,23 @@ movfr2cf 0000 00010001 01001 10100 ..... 00 ... @fmt_cdfj
movcf2fr 0000 00010001 01001 10101 00 ... ..... @fmt_fdcj
movgr2cf 0000 00010001 01001 10110 ..... 00 ... @fmt_cdrj
movcf2gr 0000 00010001 01001 10111 00 ... ..... @fmt_rdcj
+
+#
+# Floating point load/store instruction
+#
+fld_s 0010 101100 ............ ..... ..... @fmt_fdrjsi12
+fst_s 0010 101101 ............ ..... ..... @fmt_fdrjsi12
+fld_d 0010 101110 ............ ..... ..... @fmt_fdrjsi12
+fst_d 0010 101111 ............ ..... ..... @fmt_fdrjsi12
+fldx_s 0011 10000011 00000 ..... ..... ..... @fmt_fdrjrk
+fldx_d 0011 10000011 01000 ..... ..... ..... @fmt_fdrjrk
+fstx_s 0011 10000011 10000 ..... ..... ..... @fmt_fdrjrk
+fstx_d 0011 10000011 11000 ..... ..... ..... @fmt_fdrjrk
+fldgt_s 0011 10000111 01000 ..... ..... ..... @fmt_fdrjrk
+fldgt_d 0011 10000111 01001 ..... ..... ..... @fmt_fdrjrk
+fldle_s 0011 10000111 01010 ..... ..... ..... @fmt_fdrjrk
+fldle_d 0011 10000111 01011 ..... ..... ..... @fmt_fdrjrk
+fstgt_s 0011 10000111 01100 ..... ..... ..... @fmt_fdrjrk
+fstgt_d 0011 10000111 01101 ..... ..... ..... @fmt_fdrjrk
+fstle_s 0011 10000111 01110 ..... ..... ..... @fmt_fdrjrk
+fstle_d 0011 10000111 01111 ..... ..... ..... @fmt_fdrjrk
@@ -147,6 +147,19 @@ enum {
/* load/store opcodes */
enum {
+ LA_OPC_FLDX_S = (0x07060 << 15),
+ LA_OPC_FLDX_D = (0x07068 << 15),
+ LA_OPC_FSTX_S = (0x07070 << 15),
+ LA_OPC_FSTX_D = (0x07078 << 15),
+ LA_OPC_FLDGT_S = (0x070E8 << 15),
+ LA_OPC_FLDGT_D = (0x070E9 << 15),
+ LA_OPC_FLDLE_S = (0x070EA << 15),
+ LA_OPC_FLDLE_D = (0x070EB << 15),
+ LA_OPC_FSTGT_S = (0x070EC << 15),
+ LA_OPC_FSTGT_D = (0x070ED << 15),
+ LA_OPC_FSTLE_S = (0x070EE << 15),
+ LA_OPC_FSTLE_D = (0x070EF << 15),
+
LA_OPC_LD_B = (0x0A0 << 22),
LA_OPC_LD_H = (0x0A1 << 22),
LA_OPC_LD_W = (0x0A2 << 22),
@@ -158,6 +171,10 @@ enum {
LA_OPC_LD_BU = (0x0A8 << 22),
LA_OPC_LD_HU = (0x0A9 << 22),
LA_OPC_LD_WU = (0x0AA << 22),
+ LA_OPC_FLD_S = (0x0AC << 22),
+ LA_OPC_FST_S = (0x0AD << 22),
+ LA_OPC_FLD_D = (0x0AE << 22),
+ LA_OPC_FST_D = (0x0AF << 22),
LA_OPC_LL_W = (0x20 << 24),
LA_OPC_LL_D = (0x22 << 24),
@@ -2209,3 +2209,108 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
tcg_temp_free_i32(cj);
return true;
}
+
+/* Floating point load/store instruction translation */
+static bool trans_fld_s(DisasContext *ctx, arg_fld_s *a)
+{
+ gen_loongarch_fldst(ctx, LA_OPC_FLD_S, a->fd, a->rj, a->si12);
+ return true;
+}
+
+static bool trans_fst_s(DisasContext *ctx, arg_fst_s *a)
+{
+ gen_loongarch_fldst(ctx, LA_OPC_FST_S, a->fd, a->rj, a->si12);
+ return true;
+}
+
+static bool trans_fld_d(DisasContext *ctx, arg_fld_d *a)
+{
+ gen_loongarch_fldst(ctx, LA_OPC_FLD_D, a->fd, a->rj, a->si12);
+ return true;
+}
+
+static bool trans_fst_d(DisasContext *ctx, arg_fst_d *a)
+{
+ gen_loongarch_fldst(ctx, LA_OPC_FST_D, a->fd, a->rj, a->si12);
+ return true;
+}
+
+static bool trans_fldx_s(DisasContext *ctx, arg_fldx_s *a)
+{
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FLDX_S, a->fd, 0, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fldx_d(DisasContext *ctx, arg_fldx_d *a)
+{
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FLDX_D, a->fd, 0, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fstx_s(DisasContext *ctx, arg_fstx_s *a)
+{
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FSTX_S, 0, a->fd, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fstx_d(DisasContext *ctx, arg_fstx_d *a)
+{
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FSTX_D, 0, a->fd, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fldgt_s(DisasContext *ctx, arg_fldgt_s *a)
+{
+ ASRTGT;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FLDGT_S, a->fd, 0, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fldgt_d(DisasContext *ctx, arg_fldgt_d *a)
+{
+ ASRTGT;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FLDGT_D, a->fd, 0, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fldle_s(DisasContext *ctx, arg_fldle_s *a)
+{
+ ASRTLE;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FLDLE_S, a->fd, 0, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fldle_d(DisasContext *ctx, arg_fldle_d *a)
+{
+ ASRTLE;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FLDLE_D, a->fd, 0, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fstgt_s(DisasContext *ctx, arg_fstgt_s *a)
+{
+ ASRTGT;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FSTGT_S, 0, a->fd, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fstgt_d(DisasContext *ctx, arg_fstgt_d *a)
+{
+ ASRTGT;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FSTGT_D, 0, a->fd, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fstle_s(DisasContext *ctx, arg_fstle_s *a)
+{
+ ASRTLE;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FSTLE_S, 0, a->fd, a->rj, a->rk);
+ return true;
+}
+
+static bool trans_fstle_d(DisasContext *ctx, arg_fstle_d *a)
+{
+ ASRTLE;
+ gen_loongarch_fldst_extra(ctx, LA_OPC_FSTLE_D, 0, a->fd, a->rj, a->rk);
+ return true;
+}
@@ -2147,6 +2147,122 @@ static void gen_loongarch_fp_mov(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t0);
}
+/* floating point load/store */
+static void gen_loongarch_fp_ldst(DisasContext *ctx, uint32_t opc,
+ int ft, TCGv t0)
+{
+ switch (opc) {
+ case LA_OPC_FLD_S:
+ {
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
+ gen_store_fpr32(ctx, fp0, ft);
+ tcg_temp_free_i32(fp0);
+ }
+ break;
+ case LA_OPC_FST_S:
+ {
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ gen_load_fpr32(ctx, fp0, ft);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free_i32(fp0);
+ }
+ break;
+ case LA_OPC_FLD_D:
+ {
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_store_fpr64(ctx, fp0, ft);
+ tcg_temp_free_i64(fp0);
+ }
+ break;
+ case LA_OPC_FST_D:
+ {
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ gen_load_fpr64(ctx, fp0, ft);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free_i64(fp0);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_INE);
+ break;
+ }
+}
+
+static void gen_loongarch_fldst(DisasContext *ctx, uint32_t op, int fd,
+ int rj, int16_t imm)
+{
+ TCGv t0 = tcg_temp_new();
+ check_fpu_enabled(ctx);
+ gen_base_offset_addr(ctx, t0, rj, imm);
+ gen_loongarch_fp_ldst(ctx, op, fd, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_loongarch_fldst_extra(DisasContext *ctx, uint32_t opc,
+ int fld, int fst, int base, int index)
+{
+ TCGv t0 = tcg_temp_new();
+
+ if (base == 0) {
+ gen_load_gpr(t0, index);
+ } else if (index == 0) {
+ gen_load_gpr(t0, base);
+ } else {
+ gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
+ }
+
+ switch (opc) {
+ case LA_OPC_FLDX_S:
+ case LA_OPC_FLDGT_S:
+ case LA_OPC_FLDLE_S:
+ {
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_trunc_tl_i32(fp0, t0);
+ gen_store_fpr32(ctx, fp0, fld);
+ tcg_temp_free_i32(fp0);
+ }
+ break;
+ case LA_OPC_FLDX_D:
+ case LA_OPC_FLDGT_D:
+ case LA_OPC_FLDLE_D:
+ {
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
+ gen_store_fpr64(ctx, fp0, fld);
+ tcg_temp_free_i64(fp0);
+ }
+ break;
+ case LA_OPC_FSTX_S:
+ case LA_OPC_FSTGT_S:
+ case LA_OPC_FSTLE_S:
+ {
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ gen_load_fpr32(ctx, fp0, fst);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
+ tcg_temp_free_i32(fp0);
+ }
+ break;
+ case LA_OPC_FSTX_D:
+ case LA_OPC_FSTGT_D:
+ case LA_OPC_FSTLE_D:
+ {
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ gen_load_fpr64(ctx, fp0, fst);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
+ tcg_temp_free_i64(fp0);
+ }
+ break;
+ }
+ tcg_temp_free(t0);
+}
+
static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
{
}
This patch implement floating point load/store instruction translation. This includes: - FLD.{S/D}, FST.{S/D} - FLDX.{S/D}, FSTX.{S/D} - FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/insns.decode | 24 +++++++++ target/loongarch/instmap.h | 17 +++++++ target/loongarch/trans.inc.c | 105 ++++++++++++++++++++++++++++++++++++++ target/loongarch/translate.c | 116 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 262 insertions(+)