diff mbox series

[03/31] target/loongarch: Set default csr values.

Message ID 1634628917-10031-4-git-send-email-yangxiaojuan@loongson.cn (mailing list archive)
State New, archived
Headers show
Series Add Loongarch softmmu support. | expand

Commit Message

Xiaojuan Yang Oct. 19, 2021, 7:34 a.m. UTC 
This patch set default csr values Mainly used for
cpu_initfn and cpu_reset.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++
 target/loongarch/cpu.h |  6 ++++++
 2 files changed, 46 insertions(+)

Comments

Richard Henderson Oct. 19, 2021, 7:18 p.m. UTC | #1 
On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
> +#ifndef CONFIG_USER_ONLY
> +static void set_loongarch_csr(CPULoongArchState *env)
> +{
> +    uint64_t t;
> +
> +    t = FIELD_DP64(0, CSR_PRCFG1, SAVE_NUM, 8);
> +    t = FIELD_DP64(t, CSR_PRCFG1, TIMER_BITS, 0x2f);
> +    t = FIELD_DP64(t, CSR_PRCFG1, VSMAX, 0x7);
> +    env->CSR_PRCFG1 = t;
> +
> +    env->CSR_PRCFG2 = 0x3ffff000;
> +
> +    t = FIELD_DP64(0, CSR_PRCFG3, TLB_TYPE, 2);
> +    t = FIELD_DP64(t, CSR_PRCFG3, MTLB_ENTRY, 0x3f);
> +    t = FIELD_DP64(t, CSR_PRCFG3, STLB_WAYS, 0x7);
> +    t = FIELD_DP64(t, CSR_PRCFG3, STLB_SETS, 0x8);
> +    env->CSR_PRCFG3 = t;
> +
> +    t = FIELD_DP64(0, CSR_CRMD, PLV, 0);
> +    t = FIELD_DP64(t, CSR_CRMD, IE, 0);
> +    t = FIELD_DP64(t, CSR_CRMD, DA, 1);
> +    t = FIELD_DP64(t, CSR_CRMD, PG, 0);
> +    t = FIELD_DP64(t, CSR_CRMD, DATF, 1);
> +    t = FIELD_DP64(t, CSR_CRMD, DATM, 1);
> +    env->CSR_CRMD = t;
> +
> +    env->CSR_ECFG = FIELD_DP64(0, CSR_ECFG, VS, 7);
> +    env->CSR_STLBPS  = 0xe;
> +    env->CSR_RVACFG = 0x0;
> +    env->CSR_ASID = 0xa0000;
> +    env->CSR_ERA = env->pc;
> +}
> +#endif
> +
>   /* LoongArch CPU definitions */
>   static void loongarch_3a5000_initfn(Object *obj)
>   {
> @@ -113,6 +147,9 @@ static void loongarch_3a5000_initfn(Object *obj)
>       CPULoongArchState *env = &cpu->env;
>   
>       set_loongarch_cpucfg(env);
> +#ifndef CONFIG_USER_ONLY
> +    set_loongarch_csr(env);
> +#endif
>   }
>   
>   static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
> @@ -140,6 +177,9 @@ static void loongarch_cpu_reset(DeviceState *dev)
>       lacc->parent_reset(dev);
>   
>       set_loongarch_cpucfg(env);
> +#ifndef CONFIG_USER_ONLY
> +    set_loongarch_csr(env);
> +#endif

As I said vs patch 2, I think you'll want to set all of these unconditionally.


r~
diff mbox series

Patch

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index e9f67cf976..57f9264c1f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -106,6 +106,40 @@  static void set_loongarch_cpucfg(CPULoongArchState *env)
     env->cpucfg[20] = 0x60f000f;
 }
 
+#ifndef CONFIG_USER_ONLY
+static void set_loongarch_csr(CPULoongArchState *env)
+{
+    uint64_t t;
+
+    t = FIELD_DP64(0, CSR_PRCFG1, SAVE_NUM, 8);
+    t = FIELD_DP64(t, CSR_PRCFG1, TIMER_BITS, 0x2f);
+    t = FIELD_DP64(t, CSR_PRCFG1, VSMAX, 0x7);
+    env->CSR_PRCFG1 = t;
+
+    env->CSR_PRCFG2 = 0x3ffff000;
+
+    t = FIELD_DP64(0, CSR_PRCFG3, TLB_TYPE, 2);
+    t = FIELD_DP64(t, CSR_PRCFG3, MTLB_ENTRY, 0x3f);
+    t = FIELD_DP64(t, CSR_PRCFG3, STLB_WAYS, 0x7);
+    t = FIELD_DP64(t, CSR_PRCFG3, STLB_SETS, 0x8);
+    env->CSR_PRCFG3 = t;
+
+    t = FIELD_DP64(0, CSR_CRMD, PLV, 0);
+    t = FIELD_DP64(t, CSR_CRMD, IE, 0);
+    t = FIELD_DP64(t, CSR_CRMD, DA, 1);
+    t = FIELD_DP64(t, CSR_CRMD, PG, 0);
+    t = FIELD_DP64(t, CSR_CRMD, DATF, 1);
+    t = FIELD_DP64(t, CSR_CRMD, DATM, 1);
+    env->CSR_CRMD = t;
+
+    env->CSR_ECFG = FIELD_DP64(0, CSR_ECFG, VS, 7);
+    env->CSR_STLBPS  = 0xe;
+    env->CSR_RVACFG = 0x0;
+    env->CSR_ASID = 0xa0000;
+    env->CSR_ERA = env->pc;
+}
+#endif
+
 /* LoongArch CPU definitions */
 static void loongarch_3a5000_initfn(Object *obj)
 {
@@ -113,6 +147,9 @@  static void loongarch_3a5000_initfn(Object *obj)
     CPULoongArchState *env = &cpu->env;
 
     set_loongarch_cpucfg(env);
+#ifndef CONFIG_USER_ONLY
+    set_loongarch_csr(env);
+#endif
 }
 
 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
@@ -140,6 +177,9 @@  static void loongarch_cpu_reset(DeviceState *dev)
     lacc->parent_reset(dev);
 
     set_loongarch_cpucfg(env);
+#ifndef CONFIG_USER_ONLY
+    set_loongarch_csr(env);
+#endif
     env->fcsr0_mask = 0x1f1f031f;
     env->fcsr0 = 0x0;
 
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index a4991f9481..5aa0c75ad9 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -12,6 +12,7 @@ 
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"
 #include "hw/registerfields.h"
+#include "cpu-csr.h"
 
 #define TCG_GUEST_DEFAULT_MO (0)
 
@@ -68,6 +69,11 @@  struct CPULoongArchState {
     uint64_t llval;
 
     uint64_t badaddr;
+
+#ifndef CONFIG_USER_ONLY
+    /* LoongArch CSR registers */
+    CPU_LOONGARCH_CSR
+#endif
 };
 
 /**