From patchwork Tue Oct 19 07:34:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaojuan Yang X-Patchwork-Id: 12568881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65AA9C433EF for ; Tue, 19 Oct 2021 07:46:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1CCB3611EF for ; Tue, 19 Oct 2021 07:46:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1CCB3611EF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:33798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcjpc-0004Wf-4O for qemu-devel@archiver.kernel.org; Tue, 19 Oct 2021 03:46:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcjex-0001GQ-4t for qemu-devel@nongnu.org; Tue, 19 Oct 2021 03:35:43 -0400 Received: from mail.loongson.cn ([114.242.206.163]:34692 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcjes-0004OH-DQ for qemu-devel@nongnu.org; Tue, 19 Oct 2021 03:35:42 -0400 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxP2s1dW5h3HwcAA--.43474S5; Tue, 19 Oct 2021 15:35:26 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Subject: [PATCH 03/31] target/loongarch: Set default csr values. Date: Tue, 19 Oct 2021 15:34:49 +0800 Message-Id: <1634628917-10031-4-git-send-email-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1634628917-10031-1-git-send-email-yangxiaojuan@loongson.cn> References: <1634628917-10031-1-git-send-email-yangxiaojuan@loongson.cn> X-CM-TRANSID: AQAAf9DxP2s1dW5h3HwcAA--.43474S5 X-Coremail-Antispam: 1UD129KBjvJXoWxGry5Gr1fXFyrZFy8Gw13CFg_yoW5Xw4xpr 9rur90yr4xtrsrA3s3Aas8Wrn8Zw4xC34Iva9Ikw1vkFW7Xr1fXFWkt397GF9rA34rAFWI 9Fn7AayUWF4DZ3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@loongson.cn, mst@redhat.com, philmd@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, peterx@redhat.com, f4bug@amsat.org, yangxiaojuan@loongson.cn, alistair.francis@wdc.com, maobibo@loongson.cn, gaosong@loongson.cn, pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, bmeng.cn@gmail.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch set default csr values Mainly used for cpu_initfn and cpu_reset. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ target/loongarch/cpu.h | 6 ++++++ 2 files changed, 46 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e9f67cf976..57f9264c1f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -106,6 +106,40 @@ static void set_loongarch_cpucfg(CPULoongArchState *env) env->cpucfg[20] = 0x60f000f; } +#ifndef CONFIG_USER_ONLY +static void set_loongarch_csr(CPULoongArchState *env) +{ + uint64_t t; + + t = FIELD_DP64(0, CSR_PRCFG1, SAVE_NUM, 8); + t = FIELD_DP64(t, CSR_PRCFG1, TIMER_BITS, 0x2f); + t = FIELD_DP64(t, CSR_PRCFG1, VSMAX, 0x7); + env->CSR_PRCFG1 = t; + + env->CSR_PRCFG2 = 0x3ffff000; + + t = FIELD_DP64(0, CSR_PRCFG3, TLB_TYPE, 2); + t = FIELD_DP64(t, CSR_PRCFG3, MTLB_ENTRY, 0x3f); + t = FIELD_DP64(t, CSR_PRCFG3, STLB_WAYS, 0x7); + t = FIELD_DP64(t, CSR_PRCFG3, STLB_SETS, 0x8); + env->CSR_PRCFG3 = t; + + t = FIELD_DP64(0, CSR_CRMD, PLV, 0); + t = FIELD_DP64(t, CSR_CRMD, IE, 0); + t = FIELD_DP64(t, CSR_CRMD, DA, 1); + t = FIELD_DP64(t, CSR_CRMD, PG, 0); + t = FIELD_DP64(t, CSR_CRMD, DATF, 1); + t = FIELD_DP64(t, CSR_CRMD, DATM, 1); + env->CSR_CRMD = t; + + env->CSR_ECFG = FIELD_DP64(0, CSR_ECFG, VS, 7); + env->CSR_STLBPS = 0xe; + env->CSR_RVACFG = 0x0; + env->CSR_ASID = 0xa0000; + env->CSR_ERA = env->pc; +} +#endif + /* LoongArch CPU definitions */ static void loongarch_3a5000_initfn(Object *obj) { @@ -113,6 +147,9 @@ static void loongarch_3a5000_initfn(Object *obj) CPULoongArchState *env = &cpu->env; set_loongarch_cpucfg(env); +#ifndef CONFIG_USER_ONLY + set_loongarch_csr(env); +#endif } static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) @@ -140,6 +177,9 @@ static void loongarch_cpu_reset(DeviceState *dev) lacc->parent_reset(dev); set_loongarch_cpucfg(env); +#ifndef CONFIG_USER_ONLY + set_loongarch_csr(env); +#endif env->fcsr0_mask = 0x1f1f031f; env->fcsr0 = 0x0; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index a4991f9481..5aa0c75ad9 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -12,6 +12,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "hw/registerfields.h" +#include "cpu-csr.h" #define TCG_GUEST_DEFAULT_MO (0) @@ -68,6 +69,11 @@ struct CPULoongArchState { uint64_t llval; uint64_t badaddr; + +#ifndef CONFIG_USER_ONLY + /* LoongArch CSR registers */ + CPU_LOONGARCH_CSR +#endif }; /**