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Mon, 01 Nov 2021 06:13:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mhTzl-0005uX-RD for qemu-devel@nongnu.org; Mon, 01 Nov 2021 05:52:50 -0400 Received: from mail.loongson.cn ([114.242.206.163]:50746 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mhTzf-0008DE-4h for qemu-devel@nongnu.org; Mon, 01 Nov 2021 05:52:49 -0400 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxn2u3uH9hbKIjAA--.55994S17; Mon, 01 Nov 2021 17:52:24 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Subject: [PATCH v8 15/29] target/loongarch: Add branch instruction translation Date: Mon, 1 Nov 2021 17:51:37 +0800 Message-Id: <1635760311-20015-16-git-send-email-gaosong@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1635760311-20015-1-git-send-email-gaosong@loongson.cn> References: <1635760311-20015-1-git-send-email-gaosong@loongson.cn> X-CM-TRANSID: AQAAf9Dxn2u3uH9hbKIjAA--.55994S17 X-Coremail-Antispam: 1UD129KBjvJXoW3JFWDtr4DCFW5CF4DAF4Dtwb_yoWxGr47pr 1UCryUKrWkJry3Jrn5tw45Xry5Jrs8Gw17GrW3twn3XF42q3WUAF18AryUKF4jv34kZry8 tF4rAryUKFy8XwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@loongson.cn, philmd@redhat.com, i.qemu@xen0n.name, richard.henderson@linaro.org, laurent@vivier.eu, peterx@redhat.com, f4bug@amsat.org, yangxiaojuan@loongson.cn, alistair.francis@wdc.com, maobibo@loongson.cn, pbonzini@redhat.com, bmeng.cn@gmail.com, alex.bennee@linaro.org, gaosong@loongson.cn Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Reviewed-by: Richard Henderson Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang --- target/loongarch/insn_trans/trans_branch.c | 85 ++++++++++++++++++++++++++++++ target/loongarch/insns.decode | 30 +++++++++++ target/loongarch/translate.c | 1 + 3 files changed, 116 insertions(+) create mode 100644 target/loongarch/insn_trans/trans_branch.c diff --git a/target/loongarch/insn_trans/trans_branch.c b/target/loongarch/insn_trans/trans_branch.c new file mode 100644 index 0000000..77a6ae6 --- /dev/null +++ b/target/loongarch/insn_trans/trans_branch.c @@ -0,0 +1,85 @@ +/* + * LoongArch translate functions + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +static bool trans_b(DisasContext *ctx, arg_b *a) +{ + gen_goto_tb(ctx, 0, ctx->base.pc_next + (a->offs << 2)); + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} + +static bool trans_bl(DisasContext *ctx, arg_bl *a) +{ + tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4); + gen_goto_tb(ctx, 0, ctx->base.pc_next + (a->offs << 2)); + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} + +static bool trans_jirl(DisasContext *ctx, arg_jirl *a) +{ + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + + tcg_gen_addi_tl(cpu_pc, src1, (a->offs16) << 2); + tcg_gen_movi_tl(dest, ctx->base.pc_next + 4); + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} + +static void gen_bc(DisasContext *ctx, TCGv src1, TCGv src2, + target_long offs, TCGCond cond) +{ + TCGLabel *l = gen_new_label(); + tcg_gen_brcond_tl(cond, src1, src2, l); + gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); + gen_set_label(l); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offs); + ctx->base.is_jmp = DISAS_NORETURN; +} + +static bool gen_r2_bc(DisasContext *ctx, arg_fmt_rjrdoffs16 *a, TCGCond cond) +{ + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE); + + gen_bc(ctx, src1, src2, (a->offs16 << 2), cond); + return true; +} + +static bool gen_rz_bc(DisasContext *ctx, arg_fmt_rjoffs21 *a, TCGCond cond) +{ + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + TCGv src2 = tcg_constant_tl(0); + + gen_bc(ctx, src1, src2, (a->offs21 << 2), cond); + return true; +} + +static bool gen_cz_bc(DisasContext *ctx, arg_fmt_cjoffs21 *a, TCGCond cond) +{ + TCGv src1 = tcg_temp_new(); + TCGv src2 = tcg_constant_tl(0); + + tcg_gen_ld8u_tl(src1, cpu_env, + offsetof(CPULoongArchState, cf[a->cj & 0x7])); + gen_bc(ctx, src1, src2, (a->offs21 << 2), cond); + return true; +} + +TRANS(beq, gen_r2_bc, TCG_COND_EQ) +TRANS(bne, gen_r2_bc, TCG_COND_NE) +TRANS(blt, gen_r2_bc, TCG_COND_LT) +TRANS(bge, gen_r2_bc, TCG_COND_GE) +TRANS(bltu, gen_r2_bc, TCG_COND_LTU) +TRANS(bgeu, gen_r2_bc, TCG_COND_GEU) +TRANS(beqz, gen_rz_bc, TCG_COND_EQ) +TRANS(bnez, gen_rz_bc, TCG_COND_NE) +TRANS(bceqz, gen_cz_bc, TCG_COND_EQ) +TRANS(bcnez, gen_cz_bc, TCG_COND_NE) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index ea776c2..077063e 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -38,6 +38,9 @@ %ca 15:3 %fcsrd 0:5 %fcsrs 5:5 +%offs21 0:s5 10:16 +%offs16 10:s16 +%offs 0:s10 10:16 # # Argument sets @@ -74,6 +77,11 @@ &fmt_rdcj rd cj &fmt_fdrjrk fd rj rk &fmt_fdrjsi12 fd rj si12 +&fmt_rjoffs21 rj offs21 +&fmt_cjoffs21 cj offs21 +&fmt_rdrjoffs16 rd rj offs16 +&fmt_offs offs +&fmt_rjrdoffs16 rj rd offs16 # # Formats @@ -110,6 +118,11 @@ @fmt_rdcj .... ........ ..... ..... .. ... ..... &fmt_rdcj %rd %cj @fmt_fdrjrk .... ........ ..... ..... ..... ..... &fmt_fdrjrk %fd %rj %rk @fmt_fdrjsi12 .... ...... ............ ..... ..... &fmt_fdrjsi12 %fd %rj %si12 +@fmt_rjoffs21 .... .. ................ ..... ..... &fmt_rjoffs21 %rj %offs21 +@fmt_cjoffs21 .... .. ................ .. ... ..... &fmt_cjoffs21 %cj %offs21 +@fmt_rdrjoffs16 .... .. ................ ..... ..... &fmt_rdrjoffs16 %rd %rj %offs16 +@fmt_offs .... .. .......................... &fmt_offs %offs +@fmt_rjrdoffs16 .... .. ................ ..... ..... &fmt_rjrdoffs16 %rj %rd %offs16 # # Fixed point arithmetic operation instruction @@ -448,3 +461,20 @@ fstgt_s 0011 10000111 01100 ..... ..... ..... @fmt_fdrjrk fstgt_d 0011 10000111 01101 ..... ..... ..... @fmt_fdrjrk fstle_s 0011 10000111 01110 ..... ..... ..... @fmt_fdrjrk fstle_d 0011 10000111 01111 ..... ..... ..... @fmt_fdrjrk + +# +# Branch instructions +# +beqz 0100 00 ................ ..... ..... @fmt_rjoffs21 +bnez 0100 01 ................ ..... ..... @fmt_rjoffs21 +bceqz 0100 10 ................ 00 ... ..... @fmt_cjoffs21 +bcnez 0100 10 ................ 01 ... ..... @fmt_cjoffs21 +jirl 0100 11 ................ ..... ..... @fmt_rdrjoffs16 +b 0101 00 .......................... @fmt_offs +bl 0101 01 .......................... @fmt_offs +beq 0101 10 ................ ..... ..... @fmt_rjrdoffs16 +bne 0101 11 ................ ..... ..... @fmt_rjrdoffs16 +blt 0110 00 ................ ..... ..... @fmt_rjrdoffs16 +bge 0110 01 ................ ..... ..... @fmt_rjrdoffs16 +bltu 0110 10 ................ ..... ..... @fmt_rjrdoffs16 +bgeu 0110 11 ................ ..... ..... @fmt_rjrdoffs16 diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 4c9255b..502fc9d 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -191,6 +191,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext) #include "insn_trans/trans_fcnv.c" #include "insn_trans/trans_fmov.c" #include "insn_trans/trans_fmemory.c" +#include "insn_trans/trans_branch.c" static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) {