From patchwork Thu Nov 11 01:35:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaojuan Yang X-Patchwork-Id: 12613809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E227C433F5 for ; Thu, 11 Nov 2021 01:53:28 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5E48610CB for ; Thu, 11 Nov 2021 01:53:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E5E48610CB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:40758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkzHK-0000ke-Vv for qemu-devel@archiver.kernel.org; Wed, 10 Nov 2021 20:53:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkz0Z-0005jj-4n for qemu-devel@nongnu.org; Wed, 10 Nov 2021 20:36:07 -0500 Received: from mail.loongson.cn ([114.242.206.163]:54060 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkz0U-0001jO-7d for qemu-devel@nongnu.org; Wed, 10 Nov 2021 20:36:06 -0500 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxr9Ngc4xh9RMCAA--.4955S15; Thu, 11 Nov 2021 09:35:46 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 13/30] target/loongarch: Add gdb support. Date: Thu, 11 Nov 2021 09:35:11 +0800 Message-Id: <1636594528-8175-14-git-send-email-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1636594528-8175-1-git-send-email-yangxiaojuan@loongson.cn> References: <1636594528-8175-1-git-send-email-yangxiaojuan@loongson.cn> X-CM-TRANSID: AQAAf9Dxr9Ngc4xh9RMCAA--.4955S15 X-Coremail-Antispam: 1UD129KBjvAXoWfJry7ArWDZr43GF1fWF1DAwb_yoW8JrW5Go WagFsxtr18C39Yy3WrAFn0qa9FqF1jyFs7ua43ur98Gan5C3yfGryqgwn0vFyrJrs3Wry5 J3yS9a97Wrn7Xr1fn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRUUUUUUUUU= X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Song Gao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- configs/targets/loongarch64-softmmu.mak | 1 + gdb-xml/loongarch-base64.xml | 43 +++++++++++ gdb-xml/loongarch-fpu64.xml | 57 +++++++++++++++ target/loongarch/cpu.c | 9 +++ target/loongarch/gdbstub.c | 97 +++++++++++++++++++++++++ target/loongarch/internals.h | 10 +++ target/loongarch/meson.build | 1 + 7 files changed, 218 insertions(+) create mode 100644 configs/targets/loongarch64-softmmu.mak create mode 100644 gdb-xml/loongarch-base64.xml create mode 100644 gdb-xml/loongarch-fpu64.xml create mode 100644 target/loongarch/gdbstub.c diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak new file mode 100644 index 0000000000..f33fa1590b --- /dev/null +++ b/configs/targets/loongarch64-softmmu.mak @@ -0,0 +1 @@ +TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml diff --git a/gdb-xml/loongarch-base64.xml b/gdb-xml/loongarch-base64.xml new file mode 100644 index 0000000000..f2af2a4b6e --- /dev/null +++ b/gdb-xml/loongarch-base64.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/loongarch-fpu64.xml b/gdb-xml/loongarch-fpu64.xml new file mode 100644 index 0000000000..e52cf89fbc --- /dev/null +++ b/gdb-xml/loongarch-fpu64.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index fa528d5510..c789acaf2f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -147,6 +147,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) " TLBRERA 0x%016lx" " %s exception\n", __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); } + if (cs->exception_index == EXCP_EXT_INTERRUPT && + (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))) { + cs->exception_index = EXCP_DINT; + } switch (cs->exception_index) { case EXCP_SYSCALL: @@ -173,9 +177,14 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) cause = EXCCODE_ADE; update_badinstr = 1; break; + case EXCP_DINT: + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); + goto set_DERA; case EXCP_DBP: env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); + goto set_DERA; + set_DERA: env->CSR_DERA = env->pc; env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); env->pc = env->CSR_EENTRY + 0x480; diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c new file mode 100644 index 0000000000..2fec9364de --- /dev/null +++ b/target/loongarch/gdbstub.c @@ -0,0 +1,97 @@ +/* + * LOONGARCH gdb server stub + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "internals.h" +#include "exec/gdbstub.h" +#include "exec/helper-proto.h" + +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + + if (0 <= n && n < 32) { + return gdb_get_regl(mem_buf, env->gpr[n]); + } else if (n == 32) { + return gdb_get_regl(mem_buf, env->pc); + } + return 0; +} + +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + target_ulong tmp = ldtul_p(mem_buf); + + if (0 <= n && n < 32) { + return env->gpr[n] = tmp, sizeof(target_ulong); + } else if (n == 32) { + return env->pc = tmp, sizeof(target_ulong); + } + return 0; +} + +static int loongarch_gdb_get_fpu(CPULoongArchState *env, + GByteArray *mem_buf, int n) +{ + if (0 <= n && n < 32) { + return gdb_get_reg64(mem_buf, env->fpr[n]); + } else if (32 <= n && n < 40) { + return gdb_get_reg8(mem_buf, env->cf[n - 32]); + } else if (n == 40) { + return gdb_get_reg32(mem_buf, env->fcsr0); + } + return 0; +} + +static int loongarch_gdb_set_fpu(CPULoongArchState *env, + uint8_t *mem_buf, int n) +{ + if (0 <= n && n < 32) { + return env->fpr[n] = ldq_p(mem_buf), 8; + } else if (32 <= n && n < 40) { + return env->cf[n - 32] = ldub_p(mem_buf), 1; + } else if (n == 40) { + return env->fcsr0 = ldl_p(mem_buf), 4; + } + return 0; +} + +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) +{ + gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu, + 41, "loongarch-fpu64.xml", 0); +} + +int loongarch_read_qxfer(CPUState *cs, const char *annex, uint8_t *read_buf, + unsigned long offset, unsigned long len) +{ + if (strncmp(annex, "cpucfg", sizeof("cpucfg") - 1) == 0) { + if (offset % 4 != 0 || len % 4 != 0) { + return 0; + } + + size_t i; + for (i = offset; i < offset + len; i += 4) + ((uint32_t *)read_buf)[(i - offset) / 4] = + helper_cpucfg(&(LOONGARCH_CPU(cs)->env), i / 4); + return 32 * 4; + } + return 0; +} + +int loongarch_write_qxfer(CPUState *cs, const char *annex, + const uint8_t *write_buf, unsigned long offset, + unsigned long len) +{ + return 0; +} diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 3177098337..a54e676d82 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -40,5 +40,15 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void loongarch_mmu_init(CPULoongArchState *env); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n); +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); +int loongarch_read_qxfer(CPUState *cs, const char *annex, + uint8_t *read_buf, + unsigned long offset, unsigned long len); +int loongarch_write_qxfer(CPUState *cs, const char *annex, + const uint8_t *write_buf, + unsigned long offset, unsigned long len); + +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs); #endif diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build index 080d6297de..732f87e318 100644 --- a/target/loongarch/meson.build +++ b/target/loongarch/meson.build @@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files( 'fpu_helper.c', 'op_helper.c', 'translate.c', + 'gdbstub.c', )) loongarch_tcg_ss.add(zlib)