From patchwork Thu Nov 11 01:35:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaojuan Yang X-Patchwork-Id: 12613811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63F5EC433EF for ; Thu, 11 Nov 2021 01:54:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BFE54610CB for ; Thu, 11 Nov 2021 01:54:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BFE54610CB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:43166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkzIF-0002OW-VA for qemu-devel@archiver.kernel.org; Wed, 10 Nov 2021 20:54:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkz0d-0005xR-Di for qemu-devel@nongnu.org; Wed, 10 Nov 2021 20:36:11 -0500 Received: from mail.loongson.cn ([114.242.206.163]:54154 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkz0a-0001oz-Kc for qemu-devel@nongnu.org; Wed, 10 Nov 2021 20:36:11 -0500 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxr9Ngc4xh9RMCAA--.4955S20; Thu, 11 Nov 2021 09:35:54 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 18/30] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Date: Thu, 11 Nov 2021 09:35:16 +0800 Message-Id: <1636594528-8175-19-git-send-email-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1636594528-8175-1-git-send-email-yangxiaojuan@loongson.cn> References: <1636594528-8175-1-git-send-email-yangxiaojuan@loongson.cn> X-CM-TRANSID: AQAAf9Dxr9Ngc4xh9RMCAA--.4955S20 X-Coremail-Antispam: 1UD129KBjvJXoW3JFW7ZF17Cry3AF13Jw4UXFb_yoW3JF1fpF 9ruFWkKr48Wr4xWrs7Jas8XFn3Jwn7WFy7ZFWS9a4FkF47tw1Yvr1vyrZFvFyUJ3yktFyY vF95Xw12qF4UZw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Song Gao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch realize the IPI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/ipi.c | 144 +++++++++++++++++++++++++++++++ hw/loongarch/ls3a5000_virt.c | 1 + hw/loongarch/meson.build | 2 +- include/hw/loongarch/gipi.h | 37 ++++++++ include/hw/loongarch/loongarch.h | 4 + target/loongarch/cpu.h | 1 + 6 files changed, 188 insertions(+), 1 deletion(-) create mode 100644 hw/loongarch/ipi.c create mode 100644 include/hw/loongarch/gipi.h diff --git a/hw/loongarch/ipi.c b/hw/loongarch/ipi.c new file mode 100644 index 0000000000..4902205ff5 --- /dev/null +++ b/hw/loongarch/ipi.c @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch ipi interrupt support + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "sysemu/sysemu.h" +#include "sysemu/cpus.h" +#include "cpu.h" +#include "qemu/log.h" +#include "hw/loongarch/loongarch.h" +#include "migration/vmstate.h" + +static const VMStateDescription vmstate_gipi_core = { + .name = "gipi-single", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT32(status, gipi_core), + VMSTATE_UINT32(en, gipi_core), + VMSTATE_UINT32(set, gipi_core), + VMSTATE_UINT32(clear, gipi_core), + VMSTATE_UINT64_ARRAY(buf, gipi_core, MAX_GIPI_MBX_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_gipi = { + .name = "gipi", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(core, gipiState, MAX_GIPI_CORE_NUM, 0, + vmstate_gipi_core, gipi_core), + VMSTATE_END_OF_LIST() + } +}; + +static void gipi_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + gipi_core *s = opaque; + void *pbuf; + + if (size != 4) { + hw_error("size not 4"); + } + addr &= 0xff; + switch (addr) { + case CORE_STATUS_OFF: + hw_error("CORE_SET_OFF Can't be write\n"); + break; + case CORE_EN_OFF: + s->en = val; + break; + case CORE_SET_OFF: + s->status |= val; + if (s->status != 0) { + qemu_irq_raise(s->irq); + } + break; + case CORE_CLEAR_OFF: + s->status ^= val; + if (s->status == 0) { + qemu_irq_lower(s->irq); + } + break; + case CORE_BUF_20 ... CORE_BUF_38: + pbuf = (void *)s->buf + (addr - 0x20); + *(unsigned int *)pbuf = val; + break; + default: + break; + } +} + +static uint64_t gipi_readl(void *opaque, hwaddr addr, unsigned size) +{ + gipi_core *s = opaque; + uint64_t ret = 0; + void *pbuf; + + addr &= 0xff; + if (size != 4) { + hw_error("size not 4 %d\n", size); + } + switch (addr) { + case CORE_STATUS_OFF: + ret = s->status; + break; + case CORE_EN_OFF: + ret = s->en; + break; + case CORE_SET_OFF: + ret = 0; + break; + case CORE_CLEAR_OFF: + ret = 0; + break; + case CORE_BUF_20 ... CORE_BUF_38: + pbuf = (void *)s->buf + (addr - 0x20); + ret = *(unsigned int *)pbuf; + break; + default: + break; + } + + return ret; +} + +static const MemoryRegionOps gipi_ops = { + .read = gipi_readl, + .write = gipi_writel, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +int cpu_init_ipi(LoongArchMachineState *lams, qemu_irq parent, int cpu) +{ + int core_num = cpu % 4; + hwaddr addr; + MemoryRegion *region; + char str[32]; + + if (lams->gipi == NULL) { + lams->gipi = g_malloc0(sizeof(gipiState)); + vmstate_register(NULL, 0, &vmstate_gipi, lams->gipi); + } + + lams->gipi->core[cpu].irq = parent; + + addr = SMP_GIPI_MAILBOX + core_num * 0x100; + region = g_new(MemoryRegion, 1); + sprintf(str, "gipi%d", cpu); + memory_region_init_io(region, NULL, &gipi_ops, + &lams->gipi->core[cpu], str, 0x100); + memory_region_add_subregion(lams->system_iocsr, addr, region); + return 0; +} diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c index 37d6b1ec88..bd79df96df 100644 --- a/hw/loongarch/ls3a5000_virt.c +++ b/hw/loongarch/ls3a5000_virt.c @@ -153,6 +153,7 @@ static void ls3a5000_virt_init(MachineState *machine) /* Init CPU internal devices */ cpu_loongarch_init_irq(cpu); cpu_loongarch_clock_init(cpu); + cpu_init_ipi(lams, env->irq[IRQ_IPI], i); qemu_register_reset(main_cpu_reset, cpu); } diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build index a972210680..1bd209c9eb 100644 --- a/hw/loongarch/meson.build +++ b/hw/loongarch/meson.build @@ -1,5 +1,5 @@ loongarch_ss = ss.source_set() loongarch_ss.add(files('loongarch_int.c')) -loongarch_ss.add(when: 'CONFIG_LOONGSON_3A5000', if_true: files('ls3a5000_virt.c')) +loongarch_ss.add(when: 'CONFIG_LOONGSON_3A5000', if_true: files('ls3a5000_virt.c', 'ipi.c')) hw_arch += {'loongarch': loongarch_ss} diff --git a/include/hw/loongarch/gipi.h b/include/hw/loongarch/gipi.h new file mode 100644 index 0000000000..244d4e3ecf --- /dev/null +++ b/include/hw/loongarch/gipi.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch ipi interrupt header files + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_GIPI_H +#define HW_LOONGARCH_GIPI_H + +#define SMP_GIPI_MAILBOX 0x1000ULL +#define CORE_STATUS_OFF 0x0 +#define CORE_EN_OFF 0x4 +#define CORE_SET_OFF 0x8 +#define CORE_CLEAR_OFF 0xc +#define CORE_BUF_20 0x20 +#define CORE_BUF_28 0x28 +#define CORE_BUF_30 0x30 +#define CORE_BUF_38 0x38 + +#define MAX_GIPI_CORE_NUM 4 +#define MAX_GIPI_MBX_NUM 4 + +typedef struct gipi_core { + uint32_t status; + uint32_t en; + uint32_t set; + uint32_t clear; + uint64_t buf[MAX_GIPI_MBX_NUM]; + qemu_irq irq; +} gipi_core; + +typedef struct gipiState { + gipi_core core[MAX_GIPI_CORE_NUM]; +} gipiState; + +#endif diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h index 8538697e5f..54cc875e6d 100644 --- a/include/hw/loongarch/loongarch.h +++ b/include/hw/loongarch/loongarch.h @@ -12,6 +12,7 @@ #include "qemu-common.h" #include "hw/boards.h" #include "qemu/queue.h" +#include "hw/loongarch/gipi.h" #define LOONGARCH_MAX_VCPUS 4 #define PM_MMIO_ADDR 0x10080000UL @@ -38,6 +39,8 @@ typedef struct LoongArchMachineState { AddressSpace *address_space_iocsr; MemoryRegion *system_iocsr; + + gipiState *gipi; } LoongArchMachineState; #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson7a") @@ -45,4 +48,5 @@ DECLARE_INSTANCE_CHECKER(LoongArchMachineState, LOONGARCH_MACHINE, TYPE_LOONGARCH_MACHINE) void cpu_loongarch_init_irq(LoongArchCPU *cpu); +int cpu_init_ipi(LoongArchMachineState *lams, qemu_irq irq, int cpu); #endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 77afe9e26a..b7ef0b8b3c 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -152,6 +152,7 @@ extern const char * const fregnames[]; #define N_IRQS 14 #define IRQ_TIMER 11 +#define IRQ_IPI 12 /* * LoongArch cpu has 4 priv level, now only 2 mode used.