@@ -1,5 +1,13 @@
config LOONGSON_3A5000
bool
+ imply VGA_PCI
+ imply VIRTIO_VGA
+ imply PARALLEL
+ imply PCI_DEVICES
+ select ISA_BUS
+ select SERIAL
+ select SERIAL_ISA
+ select VIRTIO_PCI
select PCI_EXPRESS_7A
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI
@@ -10,8 +10,11 @@
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "hw/boards.h"
+#include "hw/char/serial.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
+#include "hw/irq.h"
+#include "net/net.h"
#include "sysemu/runstate.h"
#include "sysemu/reset.h"
#include "hw/loongarch/loongarch.h"
@@ -19,6 +22,7 @@
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/pci-host/ls7a.h"
+#include "hw/misc/unimp.h"
CPULoongArchState *cpu_states[LOONGARCH_MAX_VCPUS];
@@ -150,6 +154,10 @@ static void ls3a5000_irq_init(MachineState *machine, CPULoongArchState *env[])
sysbus_realize_and_unref(d, &error_fatal);
sysbus_mmio_map(d, 0, LS7A_IOAPIC_REG_BASE);
+ serial_mm_init(get_system_memory(), LS7A_UART_BASE, 0,
+ qdev_get_gpio_in(pch_pic, LS7A_UART_IRQ - 64),
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+
for (int i = 0; i < 32; i++) {
sysbus_connect_irq(d, i, lams->pch_irq[i]);
}
@@ -163,6 +171,22 @@ static void ls3a5000_irq_init(MachineState *machine, CPULoongArchState *env[])
}
}
+/* Network support */
+static void network_init(PCIBus *pci_bus)
+{
+ int i;
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
+}
+
static void ls3a5000_virt_init(MachineState *machine)
{
const char *cpu_model = machine->cpu_type;
@@ -176,6 +200,7 @@ static void ls3a5000_virt_init(MachineState *machine)
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
int i;
MemoryRegion *iomem = NULL;
+ PCIBus *pci_bus = NULL;
if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
@@ -240,9 +265,33 @@ static void ls3a5000_virt_init(MachineState *machine)
memory_region_add_subregion(address_space_mem,
PM_MMIO_ADDR, iomem);
+ /*
+ * There are some invalid guest memory access.
+ * Create some unimplemented devices to emulate this.
+ */
+ create_unimplemented_device("ls7a-lpc", 0x10002000, 0x14);
+ create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
+ create_unimplemented_device("node-bridge", 0xEFDFB000274, 0x4);
+ create_unimplemented_device("ls7a-lionlpc", 0x1fe01400, 0x38);
+ create_unimplemented_device("ls7a-node0", 0x0EFDFB000274, 0x4);
+ create_unimplemented_device("ls7a-node1", 0x1EFDFB000274, 0x4);
+ create_unimplemented_device("ls7a-node2", 0x2EFDFB000274, 0x4);
+ create_unimplemented_device("ls7a-node3", 0x3EFDFB000274, 0x4);
+
/* Initialize the IO interrupt subsystem */
ls3a5000_irq_init(machine, cpu_states);
+ /* Init the north bridge */
+ pci_bus = ls7a_init(machine, lams->pch_irq);
+
+ /* Network card */
+ network_init(pci_bus);
+
+ /* VGA setup. Don't bother loading the bios. */
+ pci_vga_init(pci_bus);
+
+ pci_create_simple(pci_bus, -1, "pci-ohci");
+
LOONGARCH_SIMPLE_MMIO_OPS(FEATURE_REG, "loongarch_feature", 0x8);
LOONGARCH_SIMPLE_MMIO_OPS(VENDOR_REG, "loongarch_vendor", 0x8);
LOONGARCH_SIMPLE_MMIO_OPS(CPUNAME_REG, "loongarch_cpuname", 0x8);
@@ -27,6 +27,38 @@ static const VMStateDescription vmstate_ls7a_pcie = {
}
};
+static PCIINTxRoute ls7a_route_intx_pin_to_irq(void *opaque, int pin)
+{
+ PCIINTxRoute route;
+
+ route.irq = pin;
+ route.mode = PCI_INTX_ENABLED;
+ return route;
+}
+
+static int pci_ls7a_map_irq(PCIDevice *d, int irq_num)
+{
+ PCIBus *bus;
+ int irq;
+
+ bus = pci_get_bus(d);
+ if (bus->parent_dev) {
+ irq = pci_swizzle_map_irq_fn(d, irq_num);
+ return irq;
+ }
+
+ irq = 64 + 16 + ((PCI_SLOT(d->devfn) * 4 + irq_num) & 0xf);
+
+ return irq;
+}
+
+static void pci_ls7a_set_irq(void *opaque, int irq_num, int level)
+{
+ LS7APCIEHost *pciehost = opaque;
+
+ qemu_set_irq(pciehost->pic[irq_num - 64], level);
+}
+
static void pci_ls7a_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
@@ -63,11 +95,13 @@ static void ls7a_pciehost_realize(DeviceState *dev, Error **errp)
PCIExpressHost *e = PCIE_HOST_BRIDGE(dev);
PCIHostState *phb = PCI_HOST_BRIDGE(e);
- phb->bus = pci_register_root_bus(dev, "pcie.0", NULL,
- NULL, pciehost,
+ phb->bus = pci_register_root_bus(dev, "pcie.0", pci_ls7a_set_irq,
+ pci_ls7a_map_irq, pciehost,
get_system_memory(), get_system_io(),
PCI_DEVFN(1, 0), 128, TYPE_PCIE_BUS);
+ pci_bus_set_route_irq_fn(phb->bus, ls7a_route_intx_pin_to_irq);
+
memory_region_init_io(&pciehost->pci_conf, OBJECT(dev),
&pci_ls7a_config_ops, phb->bus,
"ls7a_pci_conf", HT1LO_PCICFG_SIZE);
@@ -27,6 +27,10 @@
#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL
+#define LOONGARCH_PCH_IRQ_BASE 64
+#define LS7A_UART_IRQ (LOONGARCH_PCH_IRQ_BASE + 2)
+#define LS7A_UART_BASE 0x1fe001e0
+
typedef struct LS7APCIState LS7APCIState;
typedef struct LS7APCIEHost {
PCIExpressHost parent_obj;
@@ -60,7 +60,8 @@ typedef struct QDevAlias
QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \
QEMU_ARCH_MIPS | QEMU_ARCH_PPC | \
QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \
- QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA)
+ QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA | \
+ QEMU_ARCH_LOONGARCH)
#define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)
#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)