| Message ID | 17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathbern@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Hexagon: add lldb support | expand |
> -----Original Message----- > From: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> > Sent: Thursday, May 4, 2023 10:38 AM > To: qemu-devel@nongnu.org > Cc: alex.bennee@linaro.org; Brian Cain <bcain@quicinc.com>; > f4bug@amsat.org; peter.maydell@linaro.org; Taylor Simpson > <tsimpson@quicinc.com>; philmd@linaro.org; richard.henderson@linaro.org; > Laurent Vivier <laurent@vivier.eu> > Subject: [PATCH v3 5/6] Hexagon (gdbstub): add HVX support > > From: Taylor Simpson <tsimpson@quicinc.com> > > Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> > Co-authored-by: Brian Cain <bcain@quicinc.com> > Signed-off-by: Brian Cain <bcain@quicinc.com> > Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> > Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> > --- > configs/targets/hexagon-linux-user.mak | 2 +- > target/hexagon/internal.h | 2 + > target/hexagon/cpu.c | 6 ++ > target/hexagon/gdbstub.c | 68 ++++++++++++++++++ > gdb-xml/hexagon-hvx.xml | 96 ++++++++++++++++++++++++++ > 5 files changed, 173 insertions(+), 1 deletion(-) > create mode 100644 gdb-xml/hexagon-hvx.xml > > diff --git a/configs/targets/hexagon-linux-user.mak b/configs/targets/hexagon- > linux-user.mak > index fd5e222d4f..2765a4c563 100644 > --- a/configs/targets/hexagon-linux-user.mak > +++ b/configs/targets/hexagon-linux-user.mak > @@ -1,2 +1,2 @@ > TARGET_ARCH=hexagon > -TARGET_XML_FILES=gdb-xml/hexagon-core.xml > +TARGET_XML_FILES=gdb-xml/hexagon-core.xml gdb-xml/hexagon-hvx.xml > diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h > index b1bfadc3f5..d732b6bb3c 100644 > --- a/target/hexagon/internal.h > +++ b/target/hexagon/internal.h > @@ -33,6 +33,8 @@ > > int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > +int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray > *mem_buf, int n); > +int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t > *mem_buf, int n); > > void hexagon_debug_vreg(CPUHexagonState *env, int regnum); > void hexagon_debug_qreg(CPUHexagonState *env, int regnum); > diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c > index a59d964574..2e36903d9d 100644 > --- a/target/hexagon/cpu.c > +++ b/target/hexagon/cpu.c > @@ -24,6 +24,7 @@ > #include "hw/qdev-properties.h" > #include "fpu/softfloat-helpers.h" > #include "tcg/tcg.h" > +#include "exec/gdbstub.h" > > static void hexagon_v67_cpu_init(Object *obj) > { > @@ -315,6 +316,11 @@ static void hexagon_cpu_realize(DeviceState *dev, > Error **errp) > return; > } > > + gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, > + hexagon_hvx_gdb_write_register, > + NUM_VREGS + NUM_QREGS, > + "hexagon-hvx.xml", 0); > + > qemu_init_vcpu(cs); > cpu_reset(cs); > > diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c > index a06fed9f18..54d37e006e 100644 > --- a/target/hexagon/gdbstub.c > +++ b/target/hexagon/gdbstub.c > @@ -60,3 +60,71 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t > *mem_buf, int n) > > g_assert_not_reached(); > } > + > +static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n) > +{ > + int total = 0; > + int i; > + for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { > + total += gdb_get_regl(mem_buf, env->VRegs[n].uw[i]); > + } > + return total; > +} > + > +static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n) > +{ > + int total = 0; > + int i; > + for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { > + total += gdb_get_regl(mem_buf, env->QRegs[n].uw[i]); > + } > + return total; > +} > + > +int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray > *mem_buf, int n) > +{ > + if (n < NUM_VREGS) { > + return gdb_get_vreg(env, mem_buf, n); > + } > + n -= NUM_VREGS; > + > + if (n < NUM_QREGS) { > + return gdb_get_qreg(env, mem_buf, n); > + } > + > + g_assert_not_reached(); > +} > + > +static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n) > +{ > + int i; > + for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { > + env->VRegs[n].uw[i] = ldtul_p(mem_buf); > + mem_buf += 4; > + } > + return MAX_VEC_SIZE_BYTES; > +} > + > +static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) > +{ > + int i; > + for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { > + env->QRegs[n].uw[i] = ldtul_p(mem_buf); > + mem_buf += 4; > + } > + return MAX_VEC_SIZE_BYTES / 8; > +} > + > +int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t > *mem_buf, int n) > +{ > + if (n < NUM_VREGS) { > + return gdb_put_vreg(env, mem_buf, n); > + } > + n -= NUM_VREGS; > + > + if (n < NUM_QREGS) { > + return gdb_put_qreg(env, mem_buf, n); > + } > + > + g_assert_not_reached(); > +} > diff --git a/gdb-xml/hexagon-hvx.xml b/gdb-xml/hexagon-hvx.xml > new file mode 100644 > index 0000000000..5f2e220733 > --- /dev/null > +++ b/gdb-xml/hexagon-hvx.xml > @@ -0,0 +1,96 @@ > +<?xml version="1.0"?> > +<!-- > + Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved. > + > + This work is licensed under the terms of the GNU GPL, version 2 or > + (at your option) any later version. See the COPYING file in the > + top-level directory. > + > + Note: this file is intended to be use with LLDB, so it contains fields > + that may be unknown to GDB. For more information on such fields, please > + see: > + https://github.com/llvm/llvm- > project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb- > gdb-remote.txt#L738-L860 > + https://github.com/llvm/llvm- > project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plug > ins/Process/gdb-remote/ProcessGDBRemote.cpp#L4275-L4335 > +--> > + > +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> > +<feature name="org.gnu.gdb.hexagon.hvx"> > + > + <vector id="vud" type="uint64" count="16"/> > + <vector id="vd" type="int64" count="16"/> > + <vector id="vuw" type="uint32" count="32"/> > + <vector id="vw" type="int32" count="32"/> > + <vector id="vuh" type="uint16" count="64"/> > + <vector id="vh" type="int16" count="64"/> > + <vector id="vub" type="uint8" count="128"/> > + <vector id="vb" type="int8" count="128"/> > + <union id="hex_vec"> > + <field name="ud" type="vud"/> > + <field name="d" type="vd"/> > + <field name="uw" type="vuw"/> > + <field name="w" type="vw"/> > + <field name="uh" type="vuh"/> > + <field name="h" type="vh"/> > + <field name="ub" type="vub"/> > + <field name="b" type="vb"/> > + </union> > + > + <flags id="ui2" size="1"> > + <field name="0" start="0" end="0"/> > + <field name="1" start="1" end="1"/> > + </flags> > + <flags id="ui4" size="1"> > + <field name="0" start="0" end="0"/> > + <field name="1" start="1" end="1"/> > + <field name="2" start="2" end="2"/> > + <field name="3" start="3" end="3"/> > + </flags> > + <vector id="vpd" type="uint8" count="16"/> > + <vector id="vpw" type="ui4" count="32"/> > + <vector id="vph" type="ui2" count="64"/> > + <vector id="vpb" type="bool" count="128"/> > + <union id="hex_vec_pred"> > + <field name="d" type="vpd"/> > + <field name="w" type="vpw"/> > + <field name="h" type="vph"/> > + <field name="b" type="vpb"/> > + </union> > + > + <reg name="v0" bitsize="1024" offset="256" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="88"/> > + <reg name="v1" bitsize="1024" offset="384" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="89"/> > + <reg name="v2" bitsize="1024" offset="512" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="90"/> > + <reg name="v3" bitsize="1024" offset="640" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="91"/> > + <reg name="v4" bitsize="1024" offset="768" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="92"/> > + <reg name="v5" bitsize="1024" offset="896" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="93"/> > + <reg name="v6" bitsize="1024" offset="1024" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="94"/> > + <reg name="v7" bitsize="1024" offset="1152" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="95"/> > + <reg name="v8" bitsize="1024" offset="1280" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="96"/> > + <reg name="v9" bitsize="1024" offset="1408" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="97"/> > + <reg name="v10" bitsize="1024" offset="1536" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="98"/> > + <reg name="v11" bitsize="1024" offset="1664" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="99"/> > + <reg name="v12" bitsize="1024" offset="1792" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="100"/> > + <reg name="v13" bitsize="1024" offset="1920" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="101"/> > + <reg name="v14" bitsize="1024" offset="2048" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="102"/> > + <reg name="v15" bitsize="1024" offset="2176" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="103"/> > + <reg name="v16" bitsize="1024" offset="2304" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="104"/> > + <reg name="v17" bitsize="1024" offset="2432" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="105"/> > + <reg name="v18" bitsize="1024" offset="2560" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="106"/> > + <reg name="v19" bitsize="1024" offset="2688" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="107"/> > + <reg name="v20" bitsize="1024" offset="2816" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="108"/> > + <reg name="v21" bitsize="1024" offset="2944" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="109"/> > + <reg name="v22" bitsize="1024" offset="3072" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="110"/> > + <reg name="v23" bitsize="1024" offset="3200" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="111"/> > + <reg name="v24" bitsize="1024" offset="3328" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="112"/> > + <reg name="v25" bitsize="1024" offset="3456" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="113"/> > + <reg name="v26" bitsize="1024" offset="3584" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="114"/> > + <reg name="v27" bitsize="1024" offset="3712" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="115"/> > + <reg name="v28" bitsize="1024" offset="3840" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="116"/> > + <reg name="v29" bitsize="1024" offset="3968" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="117"/> > + <reg name="v30" bitsize="1024" offset="4096" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="118"/> > + <reg name="v31" bitsize="1024" offset="4224" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="119"/> > + <reg name="q0" bitsize="128" offset="4352" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="120"/> > + <reg name="q1" bitsize="128" offset="4368" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="121"/> > + <reg name="q2" bitsize="128" offset="4384" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="122"/> > + <reg name="q3" bitsize="128" offset="4400" encoding="vector" > format="hex" group="HVX Vector Registers" dwarf_regnum="123"/> > + > +</feature> > -- > 2.37.2 Reviewed-by: Brian Cain <bcain@quicinc.com>
diff --git a/configs/targets/hexagon-linux-user.mak b/configs/targets/hexagon-linux-user.mak index fd5e222d4f..2765a4c563 100644 --- a/configs/targets/hexagon-linux-user.mak +++ b/configs/targets/hexagon-linux-user.mak @@ -1,2 +1,2 @@ TARGET_ARCH=hexagon -TARGET_XML_FILES=gdb-xml/hexagon-core.xml +TARGET_XML_FILES=gdb-xml/hexagon-core.xml gdb-xml/hexagon-hvx.xml diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index b1bfadc3f5..d732b6bb3c 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -33,6 +33,8 @@ int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n); +int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n); void hexagon_debug_vreg(CPUHexagonState *env, int regnum); void hexagon_debug_qreg(CPUHexagonState *env, int regnum); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a59d964574..2e36903d9d 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -24,6 +24,7 @@ #include "hw/qdev-properties.h" #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" +#include "exec/gdbstub.h" static void hexagon_v67_cpu_init(Object *obj) { @@ -315,6 +316,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) return; } + gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, + hexagon_hvx_gdb_write_register, + NUM_VREGS + NUM_QREGS, + "hexagon-hvx.xml", 0); + qemu_init_vcpu(cs); cpu_reset(cs); diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index a06fed9f18..54d37e006e 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -60,3 +60,71 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) g_assert_not_reached(); } + +static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n) +{ + int total = 0; + int i; + for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { + total += gdb_get_regl(mem_buf, env->VRegs[n].uw[i]); + } + return total; +} + +static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n) +{ + int total = 0; + int i; + for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { + total += gdb_get_regl(mem_buf, env->QRegs[n].uw[i]); + } + return total; +} + +int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n) +{ + if (n < NUM_VREGS) { + return gdb_get_vreg(env, mem_buf, n); + } + n -= NUM_VREGS; + + if (n < NUM_QREGS) { + return gdb_get_qreg(env, mem_buf, n); + } + + g_assert_not_reached(); +} + +static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n) +{ + int i; + for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { + env->VRegs[n].uw[i] = ldtul_p(mem_buf); + mem_buf += 4; + } + return MAX_VEC_SIZE_BYTES; +} + +static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) +{ + int i; + for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { + env->QRegs[n].uw[i] = ldtul_p(mem_buf); + mem_buf += 4; + } + return MAX_VEC_SIZE_BYTES / 8; +} + +int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n) +{ + if (n < NUM_VREGS) { + return gdb_put_vreg(env, mem_buf, n); + } + n -= NUM_VREGS; + + if (n < NUM_QREGS) { + return gdb_put_qreg(env, mem_buf, n); + } + + g_assert_not_reached(); +} diff --git a/gdb-xml/hexagon-hvx.xml b/gdb-xml/hexagon-hvx.xml new file mode 100644 index 0000000000..5f2e220733 --- /dev/null +++ b/gdb-xml/hexagon-hvx.xml @@ -0,0 +1,96 @@ +<?xml version="1.0"?> +<!-- + Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved. + + This work is licensed under the terms of the GNU GPL, version 2 or + (at your option) any later version. See the COPYING file in the + top-level directory. + + Note: this file is intended to be use with LLDB, so it contains fields + that may be unknown to GDB. For more information on such fields, please + see: + https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-gdb-remote.txt#L738-L860 + https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp#L4275-L4335 +--> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.hexagon.hvx"> + + <vector id="vud" type="uint64" count="16"/> + <vector id="vd" type="int64" count="16"/> + <vector id="vuw" type="uint32" count="32"/> + <vector id="vw" type="int32" count="32"/> + <vector id="vuh" type="uint16" count="64"/> + <vector id="vh" type="int16" count="64"/> + <vector id="vub" type="uint8" count="128"/> + <vector id="vb" type="int8" count="128"/> + <union id="hex_vec"> + <field name="ud" type="vud"/> + <field name="d" type="vd"/> + <field name="uw" type="vuw"/> + <field name="w" type="vw"/> + <field name="uh" type="vuh"/> + <field name="h" type="vh"/> + <field name="ub" type="vub"/> + <field name="b" type="vb"/> + </union> + + <flags id="ui2" size="1"> + <field name="0" start="0" end="0"/> + <field name="1" start="1" end="1"/> + </flags> + <flags id="ui4" size="1"> + <field name="0" start="0" end="0"/> + <field name="1" start="1" end="1"/> + <field name="2" start="2" end="2"/> + <field name="3" start="3" end="3"/> + </flags> + <vector id="vpd" type="uint8" count="16"/> + <vector id="vpw" type="ui4" count="32"/> + <vector id="vph" type="ui2" count="64"/> + <vector id="vpb" type="bool" count="128"/> + <union id="hex_vec_pred"> + <field name="d" type="vpd"/> + <field name="w" type="vpw"/> + <field name="h" type="vph"/> + <field name="b" type="vpb"/> + </union> + + <reg name="v0" bitsize="1024" offset="256" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="88"/> + <reg name="v1" bitsize="1024" offset="384" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="89"/> + <reg name="v2" bitsize="1024" offset="512" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="90"/> + <reg name="v3" bitsize="1024" offset="640" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="91"/> + <reg name="v4" bitsize="1024" offset="768" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="92"/> + <reg name="v5" bitsize="1024" offset="896" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="93"/> + <reg name="v6" bitsize="1024" offset="1024" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="94"/> + <reg name="v7" bitsize="1024" offset="1152" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="95"/> + <reg name="v8" bitsize="1024" offset="1280" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="96"/> + <reg name="v9" bitsize="1024" offset="1408" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="97"/> + <reg name="v10" bitsize="1024" offset="1536" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="98"/> + <reg name="v11" bitsize="1024" offset="1664" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="99"/> + <reg name="v12" bitsize="1024" offset="1792" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="100"/> + <reg name="v13" bitsize="1024" offset="1920" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="101"/> + <reg name="v14" bitsize="1024" offset="2048" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="102"/> + <reg name="v15" bitsize="1024" offset="2176" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="103"/> + <reg name="v16" bitsize="1024" offset="2304" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="104"/> + <reg name="v17" bitsize="1024" offset="2432" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="105"/> + <reg name="v18" bitsize="1024" offset="2560" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="106"/> + <reg name="v19" bitsize="1024" offset="2688" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="107"/> + <reg name="v20" bitsize="1024" offset="2816" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="108"/> + <reg name="v21" bitsize="1024" offset="2944" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="109"/> + <reg name="v22" bitsize="1024" offset="3072" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="110"/> + <reg name="v23" bitsize="1024" offset="3200" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="111"/> + <reg name="v24" bitsize="1024" offset="3328" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="112"/> + <reg name="v25" bitsize="1024" offset="3456" encoding="vector" format="hex" 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