| Message ID | 1f9b7a8c8bca228529957a5ca62ad778870215ff.1733063076.git.neither@nut.email (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | tcg-plugins: add hooks for discontinuities | expand |
On Tue, Dec 3, 2024 at 4:30 AM Julian Ganz <neither@nut.email> wrote: > > We recently introduced API for registering callbacks for trap related > events as well as the corresponding hook functions. Due to differences > between architectures, the latter need to be called from target specific > code. > > This change places hooks for RISC-V targets. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 0a3ead69ea..6da9bd4629 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -34,6 +34,7 @@ > #include "debug.h" > #include "tcg/oversized-guest.h" > #include "pmp.h" > +#include "qemu/plugin.h" > > int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) > { > @@ -1806,6 +1807,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > !(env->mip & (1 << cause)); > bool vs_injected = env->hvip & (1 << cause) & env->hvien && > !(env->mip & (1 << cause)); > + uint64_t last_pc = env-> pc; > target_ulong tval = 0; > target_ulong tinst = 0; > target_ulong htval = 0; > @@ -1820,6 +1822,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > case RISCV_EXCP_SEMIHOST: > do_common_semihosting(cs); > env->pc += 4; > + qemu_plugin_vcpu_hostcall_cb(cs, last_pc, env->pc); > return; > #endif > case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: > @@ -1999,6 +2002,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) > riscv_cpu_set_mode(env, PRV_M, virt); > } > > + if (async) { > + qemu_plugin_vcpu_interrupt_cb(cs, last_pc, env->pc); > + } else { > + qemu_plugin_vcpu_exception_cb(cs, last_pc, env->pc); > + } > + > /* > * Interrupt/exception/trap delivery is asynchronous event and as per > * zicfilp spec CPU should clear up the ELP state. No harm in clearing > -- > 2.45.2 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0a3ead69ea..6da9bd4629 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -34,6 +34,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" #include "pmp.h" +#include "qemu/plugin.h" int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { @@ -1806,6 +1807,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1 << cause)); bool vs_injected = env->hvip & (1 << cause) & env->hvien && !(env->mip & (1 << cause)); + uint64_t last_pc = env-> pc; target_ulong tval = 0; target_ulong tinst = 0; target_ulong htval = 0; @@ -1820,6 +1822,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_SEMIHOST: do_common_semihosting(cs); env->pc += 4; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc, env->pc); return; #endif case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: @@ -1999,6 +2002,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_M, virt); } + if (async) { + qemu_plugin_vcpu_interrupt_cb(cs, last_pc, env->pc); + } else { + qemu_plugin_vcpu_exception_cb(cs, last_pc, env->pc); + } + /* * Interrupt/exception/trap delivery is asynchronous event and as per * zicfilp spec CPU should clear up the ELP state. No harm in clearing