| Message ID | 1fb34b3d81b3301bcc8febde9c8b40e3760b02c0.1716763435.git.balaton@eik.bme.hu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Remaining MMU clean up patches | expand |
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote: > Add a function to get key bit from SR and use it instead of open coded > version. > Nice. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > --- > target/ppc/mmu-hash32.c | 9 ++++++--- > target/ppc/mmu-hash32.h | 5 +++++ > target/ppc/mmu_common.c | 3 +-- > 3 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c > index 8a446c8a7d..93559447ff 100644 > --- a/target/ppc/mmu-hash32.c > +++ b/target/ppc/mmu-hash32.c > @@ -42,7 +42,7 @@ static int ppc_hash32_pte_prot(int mmu_idx, > { > unsigned pp, key; > > - key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); > + key = ppc_hash32_key(mmuidx_pr(mmu_idx), sr); > pp = pte.pte1 & HPTE32_R_PP; > > return ppc_hash32_prot(key, pp, !!(sr & SR32_NX)); > @@ -145,7 +145,6 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, > { > CPUState *cs = CPU(cpu); > CPUPPCState *env = &cpu->env; > - int key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); > > qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); > > @@ -206,7 +205,11 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, > cpu_abort(cs, "ERROR: insn should not need address translation\n"); > } > > - *prot = key ? PAGE_READ | PAGE_WRITE : PAGE_READ; > + if (ppc_hash32_key(mmuidx_pr(mmu_idx), sr)) { > + *prot = PAGE_READ | PAGE_WRITE; > + } else { > + *prot = PAGE_READ; > + } > if (check_prot_access_type(*prot, access_type)) { > *raddr = eaddr; > return true; > diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h > index bc4eedbecc..5902cf8333 100644 > --- a/target/ppc/mmu-hash32.h > +++ b/target/ppc/mmu-hash32.h > @@ -102,6 +102,11 @@ static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu, > stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); > } > > +static inline bool ppc_hash32_key(bool pr, target_ulong sr) > +{ > + return pr ? (sr & SR32_KP) : (sr & SR32_KS); > +} > + > static inline int ppc_hash32_prot(bool key, int pp, bool nx) > { > int prot; > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index 339df377e8..1ed2f45ac7 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -310,8 +310,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, > pr = FIELD_EX64(env->msr, MSR, PR); > > sr = env->sr[eaddr >> 28]; > - ctx->key = (((sr & 0x20000000) && pr) || > - ((sr & 0x40000000) && !pr)) ? 1 : 0; > + ctx->key = ppc_hash32_key(pr, sr); > ds = sr & SR32_T; > nx = sr & SR32_NX; > vsid = sr & SR32_VSID;
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 8a446c8a7d..93559447ff 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -42,7 +42,7 @@ static int ppc_hash32_pte_prot(int mmu_idx, { unsigned pp, key; - key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); + key = ppc_hash32_key(mmuidx_pr(mmu_idx), sr); pp = pte.pte1 & HPTE32_R_PP; return ppc_hash32_prot(key, pp, !!(sr & SR32_NX)); @@ -145,7 +145,6 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - int key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); @@ -206,7 +205,11 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, cpu_abort(cs, "ERROR: insn should not need address translation\n"); } - *prot = key ? PAGE_READ | PAGE_WRITE : PAGE_READ; + if (ppc_hash32_key(mmuidx_pr(mmu_idx), sr)) { + *prot = PAGE_READ | PAGE_WRITE; + } else { + *prot = PAGE_READ; + } if (check_prot_access_type(*prot, access_type)) { *raddr = eaddr; return true; diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index bc4eedbecc..5902cf8333 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -102,6 +102,11 @@ static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu, stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); } +static inline bool ppc_hash32_key(bool pr, target_ulong sr) +{ + return pr ? (sr & SR32_KP) : (sr & SR32_KS); +} + static inline int ppc_hash32_prot(bool key, int pp, bool nx) { int prot; diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 339df377e8..1ed2f45ac7 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -310,8 +310,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, pr = FIELD_EX64(env->msr, MSR, PR); sr = env->sr[eaddr >> 28]; - ctx->key = (((sr & 0x20000000) && pr) || - ((sr & 0x40000000) && !pr)) ? 1 : 0; + ctx->key = ppc_hash32_key(pr, sr); ds = sr & SR32_T; nx = sr & SR32_NX; vsid = sr & SR32_VSID;
Add a function to get key bit from SR and use it instead of open coded version. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- target/ppc/mmu-hash32.c | 9 ++++++--- target/ppc/mmu-hash32.h | 5 +++++ target/ppc/mmu_common.c | 3 +-- 3 files changed, 12 insertions(+), 5 deletions(-)