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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id w125sm22676221ywd.55.2016.05.24.10.19.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 May 2016 10:19:00 -0700 (PDT) From: Pranith Kumar To: Peter Maydell , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sergey Fedorov , qemu-devel@nongnu.org (open list:i386 target) Date: Tue, 24 May 2016 13:18:54 -0400 Message-Id: <20160524171856.1000-2-bobby.prani@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160524171856.1000-1-bobby.prani@gmail.com> References: <20160524171856.1000-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::244 Subject: [Qemu-devel] [RFC PATCH 1/3] Introduce TCGOpcode for fence instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This commit introduces the TCGOpcode for fence instruction. Signed-off-by: Pranith Kumar --- tcg/i386/tcg-target.inc.c | 4 ++++ tcg/tcg-opc.h | 2 ++ tcg/tcg.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 8fd37f4..238fa10 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2114,6 +2114,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_fence: + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -2179,6 +2181,8 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } }, { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } }, + { INDEX_op_fence, { } }, + #if TCG_TARGET_REG_BITS == 32 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } }, diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 6d0410c..4696cf1 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) # define IMPL64 TCG_OPF_64BIT #endif +DEF(fence, 0, 0, 0, 0) + DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) diff --git a/tcg/tcg.c b/tcg/tcg.c index b46bf1a..b5a22ba 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2443,6 +2443,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) tcg_reg_alloc_call(s, op->callo, op->calli, args, dead_args, sync_args); break; + case INDEX_op_fence: + break; default: /* Sanity check that we've not introduced any unhandled opcodes. */ if (def->flags & TCG_OPF_NOT_PRESENT) {