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[80.15.154.113]) by smtp.googlemail.com with ESMTPSA id lf9sm15133703wjc.44.2016.05.26.09.36.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 May 2016 09:36:13 -0700 (PDT) From: Alvise Rigo To: mttcg@listserver.greensocs.com, alex.bennee@linaro.org Date: Thu, 26 May 2016 18:35:44 +0200 Message-Id: <20160526163549.3276-6-a.rigo@virtualopensystems.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160526163549.3276-1-a.rigo@virtualopensystems.com> References: <20160526163549.3276-1-a.rigo@virtualopensystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [RFC 05/10] target-arm: End TB after ldrex instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, rth@twiddle.net, claudio.fontana@huawei.com, qemu-devel@nongnu.org, Alvise Rigo , cota@braap.org, serge.fdrv@gmail.com, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP A VCPU executing a ldrex instruction might query flushes to other VCPUs: in this cases, the calling VCPU uses cpu_exit to exit from the cpu loop and wait the other VCPUs to perform the flush. In order to exit from the cpu loop as soon as possible, interrupt the TB after the ldrex instruction. Signed-off-by: Alvise Rigo --- target-arm/translate-a64.c | 2 ++ target-arm/translate.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 376cb1c..2a14c14 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1875,6 +1875,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (!is_store) { s->is_ldex = true; gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); + gen_a64_set_pc_im(s->pc); + s->is_jmp = DISAS_JUMP; } else { gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); } diff --git a/target-arm/translate.c b/target-arm/translate.c index 0677e04..7c1cb19 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8807,6 +8807,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default: abort(); } + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_JUMP; } else { rm = insn & 0xf; switch (op1) {