@@ -157,6 +157,8 @@ static inline void tlb_tables_flush_bitmap(CPUState *cpu, unsigned long *bitmap)
struct TLBFlushByMMUIdxParams {
DECLARE_BITMAP(idx_to_flush, NB_MMU_MODES);
+ /* Used by tlb_flush_page_by_mmuidx */
+ target_ulong addr;
};
static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, void *opaque)
@@ -255,28 +257,13 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
tb_flush_jmp_cache(cpu, addr);
}
-void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
+static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu, void *opaque)
{
CPUArchState *env = cpu->env_ptr;
- int i, k;
- va_list argp;
-
- va_start(argp, addr);
-
- tlb_debug("addr "TARGET_FMT_lx"\n", addr);
-
- /* Check if we need to flush due to large pages. */
- if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
- tlb_debug("forced full flush ("
- TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
- env->tlb_flush_addr, env->tlb_flush_mask);
+ struct TLBFlushByMMUIdxParams *params = opaque;
+ target_ulong addr = params->addr;
+ int mmu_idx, i;
- /* Temporarily use current_cpu until tlb_flush_page_by_mmuidx
- * is reworked */
- tlb_flush_by_mmuidx(current_cpu, cpu, argp);
- va_end(argp);
- return;
- }
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
cpu->current_tb = NULL;
@@ -284,6 +271,49 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
addr &= TARGET_PAGE_MASK;
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
+ if (test_bit(mmu_idx, params->idx_to_flush)) {
+ int k;
+
+ tlb_debug("idx %d\n", mmu_idx);
+ tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
+ /* check whether there are vltb entries that need to be flushed */
+ for (k = 0; k < CPU_VTLB_SIZE; k++) {
+ tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
+ }
+ }
+ }
+
+ tb_flush_jmp_cache(cpu, addr);
+
+ g_free(params);
+}
+
+static void v_tlb_flush_page_by_mmuidx(CPUState *cpu, CPUState *target_cpu,
+ target_ulong addr, unsigned long *idxmap)
+{
+ if (!qemu_cpu_is_self(target_cpu)) {
+ struct TLBFlushByMMUIdxParams *params;
+
+ params = g_malloc(sizeof(struct TLBFlushByMMUIdxParams));
+ params->addr = addr;
+ memcpy(params->idx_to_flush, idxmap, MMUIDX_BITMAP_SIZE);
+ async_wait_run_on_cpu(target_cpu, cpu,
+ tlb_flush_page_by_mmuidx_async_work, params);
+ } else {
+ tlb_tables_flush_bitmap(cpu, idxmap);
+ }
+}
+
+void tlb_flush_page_by_mmuidx(CPUState *cpu, CPUState *target,
+ target_ulong addr, ...)
+{
+ DECLARE_BITMAP(idxmap, NB_MMU_MODES) = { 0 };
+ CPUArchState *env = target->env_ptr;
+ va_list argp;
+
+ va_start(argp, addr);
+
for (;;) {
int mmu_idx = va_arg(argp, int);
@@ -291,18 +321,24 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
break;
}
- tlb_debug("idx %d\n", mmu_idx);
+ set_bit(mmu_idx, idxmap);
+ }
- tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
+ va_end(argp);
- /* check whether there are vltb entries that need to be flushed */
- for (k = 0; k < CPU_VTLB_SIZE; k++) {
- tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
- }
+ tlb_debug("addr "TARGET_FMT_lx"\n", addr);
+
+ /* Check if we need to flush due to large pages. */
+ if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
+ tlb_debug("forced full flush ("
+ TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
+ env->tlb_flush_addr, env->tlb_flush_mask);
+
+ v_tlb_flush_by_mmuidx(cpu, target, idxmap);
+ return;
}
- va_end(argp);
- tb_flush_jmp_cache(cpu, addr);
+ v_tlb_flush_page_by_mmuidx(cpu, target, addr, idxmap);
}
static void tlb_flush_page_async_work(CPUState *cpu, void *opaque)
@@ -143,7 +143,8 @@ void tlb_flush(CPUState *cpu, int flush_global);
* Flush one page from the TLB of the specified CPU, for the specified
* MMU indexes.
*/
-void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...);
+void tlb_flush_page_by_mmuidx(CPUState *cpu, CPUState *target,
+ target_ulong addr, ...);
/**
* tlb_flush_by_mmuidx:
* @cpu: CPU whose TLB should be flushed
@@ -200,7 +201,7 @@ static inline void tlb_flush(CPUState *cpu, int flush_global)
{
}
-static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
+static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, CPUState *target,
target_ulong addr, ...)
{
}
@@ -2869,10 +2869,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (arm_is_secure_below_el3(env)) {
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
+ tlb_flush_page_by_mmuidx(cs, cs, pageaddr, ARMMMUIdx_S1SE1,
ARMMMUIdx_S1SE0, -1);
} else {
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
+ tlb_flush_page_by_mmuidx(cs, cs, pageaddr, ARMMMUIdx_S12NSE1,
ARMMMUIdx_S12NSE0, -1);
}
}
@@ -2888,7 +2888,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
+ tlb_flush_page_by_mmuidx(cs, cs, pageaddr, ARMMMUIdx_S1E2, -1);
}
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -2902,23 +2902,23 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
+ tlb_flush_page_by_mmuidx(cs, cs, pageaddr, ARMMMUIdx_S1E3, -1);
}
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
bool sec = arm_is_secure_below_el3(env);
- CPUState *other_cs;
+ CPUState *other_cs, *this_cs = ENV_GET_CPU(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
CPU_FOREACH(other_cs) {
if (sec) {
- tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
- ARMMMUIdx_S1SE0, -1);
+ tlb_flush_page_by_mmuidx(this_cs, other_cs, pageaddr,
+ ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
} else {
- tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
- ARMMMUIdx_S12NSE0, -1);
+ tlb_flush_page_by_mmuidx(this_cs, other_cs, pageaddr,
+ ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
}
}
}
@@ -2926,22 +2926,24 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
+ CPUState *other_cs, *this_cs = ENV_GET_CPU(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
CPU_FOREACH(other_cs) {
- tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
+ tlb_flush_page_by_mmuidx(this_cs, other_cs, pageaddr,
+ ARMMMUIdx_S1E2, -1);
}
}
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
+ CPUState *other_cs, *this_cs = ENV_GET_CPU(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
CPU_FOREACH(other_cs) {
- tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
+ tlb_flush_page_by_mmuidx(this_cs, other_cs, pageaddr,
+ ARMMMUIdx_S1E3, -1);
}
}
@@ -2964,13 +2966,13 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 48);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
+ tlb_flush_page_by_mmuidx(cs, cs, pageaddr, ARMMMUIdx_S2NS, -1);
}
static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
+ CPUState *other_cs, *this_cs = ENV_GET_CPU(env);
uint64_t pageaddr;
if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
@@ -2980,7 +2982,8 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 48);
CPU_FOREACH(other_cs) {
- tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
+ tlb_flush_page_by_mmuidx(this_cs, other_cs, pageaddr,
+ ARMMMUIdx_S2NS, -1);
}
}
Similarly to the previous commit, make tlb_flush_page_by_mmuidx query the flushes when targeting different VCPUs. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> --- cputlb.c | 90 ++++++++++++++++++++++++++++++++++--------------- include/exec/exec-all.h | 5 +-- target-arm/helper.c | 35 ++++++++++--------- 3 files changed, 85 insertions(+), 45 deletions(-)