From patchwork Fri Jun 17 07:20:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9182725 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 11FA36075F for ; Fri, 17 Jun 2016 07:21:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0110E26992 for ; Fri, 17 Jun 2016 07:21:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E9F882839E; Fri, 17 Jun 2016 07:21:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3FFB326992 for ; Fri, 17 Jun 2016 07:21:01 +0000 (UTC) Received: from localhost ([::1]:54454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDo5L-0006V3-Jy for patchwork-qemu-devel@patchwork.kernel.org; Fri, 17 Jun 2016 03:20:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58322) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDo4x-0006Sp-1U for qemu-devel@nongnu.org; Fri, 17 Jun 2016 03:20:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDo4q-00010N-VP for qemu-devel@nongnu.org; Fri, 17 Jun 2016 03:20:33 -0400 Received: from mga04.intel.com ([192.55.52.120]:16963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDo4q-000104-M3 for qemu-devel@nongnu.org; Fri, 17 Jun 2016 03:20:28 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP; 17 Jun 2016 00:20:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,482,1459839600"; d="scan'208";a="999589512" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.140]) by orsmga002.jf.intel.com with ESMTP; 17 Jun 2016 00:20:25 -0700 From: Haozhong Zhang To: seabios@seabios.org Date: Fri, 17 Jun 2016 15:20:10 +0800 Message-Id: <20160617072010.645-1-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.9.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.120 Subject: [Qemu-devel] [PATCH v2] fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-devel@nongnu.org, Haozhong Zhang Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP OS usually expects BIOS to set certain bits in MSR_IA32_FEATURE_CONTROL for some features (e.g. VMX and LMCE). QEMU provides a fw_cfg file "etc/msr_feature_control" to advise bits that should be set in MSR_IA32_FEATURE_CONTROL. If this file exists, SeaBIOS will set the advised bits in that MSR. Signed-off-by: Haozhong Zhang Reviewed-by: Paolo Bonzini --- Changes in v2: * Call msr_feature_control_setup() before smp_setup(). * Use wrmsr_smp() instead of wrmsr() on BSP. * Rename smp_mtrr and smp_mtrr_count to smp_msr and smp_msr_count as they are not only used for MTRR now. --- Makefile | 2 +- src/fw/msr_feature_control.c | 16 ++++++++++++++++ src/fw/paravirt.c | 3 ++- src/fw/smp.c | 20 ++++++++++---------- src/util.h | 3 +++ 5 files changed, 32 insertions(+), 12 deletions(-) create mode 100644 src/fw/msr_feature_control.c diff --git a/Makefile b/Makefile index 4930b3a..f38a075 100644 --- a/Makefile +++ b/Makefile @@ -43,7 +43,7 @@ SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c optionroms.c \ fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c fw/mtrr.c fw/xen.c \ fw/acpi.c fw/mptable.c fw/pirtable.c fw/smbios.c fw/romfile_loader.c \ hw/virtio-ring.c hw/virtio-pci.c hw/virtio-blk.c hw/virtio-scsi.c \ - hw/tpm_drivers.c + hw/tpm_drivers.c fw/msr_feature_control.c SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c DIRS=src src/hw src/fw vgasrc diff --git a/src/fw/msr_feature_control.c b/src/fw/msr_feature_control.c new file mode 100644 index 0000000..5ddc051 --- /dev/null +++ b/src/fw/msr_feature_control.c @@ -0,0 +1,16 @@ +#include "util.h" // msr_feature_control_setup, wrmsr_smp +#include "romfile.h" // romfile_find + +#define MSR_IA32_FEATURE_CONTROL 0x0000003a + +void msr_feature_control_setup(void) +{ + struct romfile_s *f = romfile_find("etc/msr_feature_control"); + if (!f) + return; + + u64 feature_control_bits; + f->copy(f, &feature_control_bits, sizeof(feature_control_bits)); + if (feature_control_bits) + wrmsr_smp(MSR_IA32_FEATURE_CONTROL, feature_control_bits); +} diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 8ed4380..dbb3406 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -149,8 +149,9 @@ qemu_platform_setup(void) smm_device_setup(); smm_setup(); - // Initialize mtrr and smp + // Initialize mtrr, msr_feature_control and smp mtrr_setup(); + msr_feature_control_setup(); smp_setup(); // Create bios tables diff --git a/src/fw/smp.c b/src/fw/smp.c index 579acdb..6e706e4 100644 --- a/src/fw/smp.c +++ b/src/fw/smp.c @@ -10,7 +10,7 @@ #include "output.h" // dprintf #include "romfile.h" // romfile_loadint #include "stacks.h" // yield -#include "util.h" // smp_setup +#include "util.h" // smp_setup, msr_feature_control_setup #include "x86.h" // wrmsr #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300) @@ -20,20 +20,20 @@ #define APIC_ENABLED 0x0100 -static struct { u32 index; u64 val; } smp_mtrr[32]; -static u32 smp_mtrr_count; +static struct { u32 index; u64 val; } smp_msr[32]; +static u32 smp_msr_count; void wrmsr_smp(u32 index, u64 val) { wrmsr(index, val); - if (smp_mtrr_count >= ARRAY_SIZE(smp_mtrr)) { + if (smp_msr_count >= ARRAY_SIZE(smp_msr)) { warn_noalloc(); return; } - smp_mtrr[smp_mtrr_count].index = index; - smp_mtrr[smp_mtrr_count].val = val; - smp_mtrr_count++; + smp_msr[smp_msr_count].index = index; + smp_msr[smp_msr_count].val = val; + smp_msr_count++; } u32 MaxCountCPUs; @@ -58,10 +58,10 @@ handle_smp(void) u8 apic_id = ebx>>24; dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=%d\n", apic_id); - // MTRR setup + // MTRR and MSR_IA32_FEATURE_CONTROL setup int i; - for (i=0; i