From patchwork Wed Jun 22 06:53:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9191953 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 33FDF60756 for ; Wed, 22 Jun 2016 06:54:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 220C428358 for ; Wed, 22 Jun 2016 06:54:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1511B283EE; Wed, 22 Jun 2016 06:54:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E357228358 for ; Wed, 22 Jun 2016 06:54:45 +0000 (UTC) Received: from localhost ([::1]:56037 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFc3g-0003cu-WE for patchwork-qemu-devel@patchwork.kernel.org; Wed, 22 Jun 2016 02:54:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51295) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFc3A-0003Zu-Vt for qemu-devel@nongnu.org; Wed, 22 Jun 2016 02:54:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFc37-0006ON-QM for qemu-devel@nongnu.org; Wed, 22 Jun 2016 02:54:12 -0400 Received: from mga02.intel.com ([134.134.136.20]:5860) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFc37-0006O9-KM for qemu-devel@nongnu.org; Wed, 22 Jun 2016 02:54:09 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 21 Jun 2016 23:54:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,508,1459839600"; d="scan'208";a="832966408" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.140]) by orsmga003.jf.intel.com with ESMTP; 21 Jun 2016 23:54:06 -0700 From: Haozhong Zhang To: seabios@seabios.org Date: Wed, 22 Jun 2016 14:53:24 +0800 Message-Id: <20160622065324.23812-1-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.9.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v3] fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Kevin O'Connor , qemu-devel@nongnu.org, Haozhong Zhang Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP OS usually expects BIOS to set certain bits in MSR_IA32_FEATURE_CONTROL for some features (e.g. VMX and LMCE). QEMU provides a fw_cfg file "etc/msr_feature_control" to advise bits that should be set in MSR_IA32_FEATURE_CONTROL. If this file exists, SeaBIOS will set the advised bits in that MSR. Signed-off-by: Haozhong Zhang Reviewed-by: Paolo Bonzini --- Changes in v3: * Move msr_feature_control_setup() to paravirt.c. Changes in v2: * Call msr_feature_control_setup() before smp_setup(). * Use wrmsr_smp() instead of wrmsr() on BSP. * Rename smp_mtrr and smp_mtrr_count to smp_msr and smp_msr_count as they are not only used for MTRR now. --- src/fw/paravirt.c | 12 +++++++++++- src/fw/smp.c | 20 ++++++++++---------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 8ed4380..73a08f0 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -131,6 +131,15 @@ qemu_preinit(void) dprintf(1, "RamSize: 0x%08x [cmos]\n", RamSize); } +#define MSR_IA32_FEATURE_CONTROL 0x0000003a + +static void msr_feature_control_setup(void) +{ + u64 feature_control_bits = romfile_loadint("etc/msr_feature_control", 0); + if (feature_control_bits) + wrmsr_smp(MSR_IA32_FEATURE_CONTROL, feature_control_bits); +} + void qemu_platform_setup(void) { @@ -149,8 +158,9 @@ qemu_platform_setup(void) smm_device_setup(); smm_setup(); - // Initialize mtrr and smp + // Initialize mtrr, msr_feature_control and smp mtrr_setup(); + msr_feature_control_setup(); smp_setup(); // Create bios tables diff --git a/src/fw/smp.c b/src/fw/smp.c index 579acdb..6e706e4 100644 --- a/src/fw/smp.c +++ b/src/fw/smp.c @@ -10,7 +10,7 @@ #include "output.h" // dprintf #include "romfile.h" // romfile_loadint #include "stacks.h" // yield -#include "util.h" // smp_setup +#include "util.h" // smp_setup, msr_feature_control_setup #include "x86.h" // wrmsr #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300) @@ -20,20 +20,20 @@ #define APIC_ENABLED 0x0100 -static struct { u32 index; u64 val; } smp_mtrr[32]; -static u32 smp_mtrr_count; +static struct { u32 index; u64 val; } smp_msr[32]; +static u32 smp_msr_count; void wrmsr_smp(u32 index, u64 val) { wrmsr(index, val); - if (smp_mtrr_count >= ARRAY_SIZE(smp_mtrr)) { + if (smp_msr_count >= ARRAY_SIZE(smp_msr)) { warn_noalloc(); return; } - smp_mtrr[smp_mtrr_count].index = index; - smp_mtrr[smp_mtrr_count].val = val; - smp_mtrr_count++; + smp_msr[smp_msr_count].index = index; + smp_msr[smp_msr_count].val = val; + smp_msr_count++; } u32 MaxCountCPUs; @@ -58,10 +58,10 @@ handle_smp(void) u8 apic_id = ebx>>24; dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=%d\n", apic_id); - // MTRR setup + // MTRR and MSR_IA32_FEATURE_CONTROL setup int i; - for (i=0; i