From patchwork Tue Oct 11 18:40:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9371593 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8E9796048F for ; Tue, 11 Oct 2016 18:41:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 83B8B289E4 for ; Tue, 11 Oct 2016 18:41:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7829E29067; Tue, 11 Oct 2016 18:41:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 17E9A289E4 for ; Tue, 11 Oct 2016 18:41:34 +0000 (UTC) Received: from localhost ([::1]:57412 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bu1zZ-0007aq-6O for patchwork-qemu-devel@patchwork.kernel.org; Tue, 11 Oct 2016 14:41:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53389) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bu1z5-0007ZT-2q for qemu-devel@nongnu.org; Tue, 11 Oct 2016 14:41:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bu1z4-0003TH-2E for qemu-devel@nongnu.org; Tue, 11 Oct 2016 14:41:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56536) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bu1z3-0003TD-OS for qemu-devel@nongnu.org; Tue, 11 Oct 2016 14:41:01 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4264E6176A; Tue, 11 Oct 2016 18:41:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476211261; bh=eHWXCkoRDHqxkFa5+8dt1aJ68lw0V6yRLNXnXjoPrh8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bazy0cjhBGDYjrKoBOoBsDB0cuHbpWNxnNt5Qw8/0u1Q59ZrxvJ/re+jNIiggNvVb QBTdjzUNkkPDNqH2bAL5SBw19UtGFQ37ThriH1a2tvSx/e0XHeCH2YjXbRiWjkooGw gIIT9thRnSufgdnhCeSCkXSOgJ22zLmnBoE2jpSI= Received: from rtp-lab-has1.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3258761707; Tue, 11 Oct 2016 18:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476211260; bh=eHWXCkoRDHqxkFa5+8dt1aJ68lw0V6yRLNXnXjoPrh8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=idOcQeveccyUYmGH/274I/YV5lkEjQ43kEOi6ieg59+QLsGRAqErpxgxCHwUcNwMg AkYunjH0nwOAFmMKxAe4H+McNe8UnfOgu/Misrk2MTahvUmgGaXr3sC9iDjkUrX2Xw ERS0uUx5VciBDLQ7KG6wkmK6OHiEBJugdCGaNSQU= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 3258761707 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Andrew Jones , qemu-devel@nongnu.org Date: Tue, 11 Oct 2016 14:40:43 -0400 Message-Id: <20161011184044.28373-2-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161011184044.28373-1-cov@codeaurora.org> References: <20161011184044.28373-1-cov@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [kvm-unit-tests PATCHv6 2/3] arm: pmu: Check cycle count increases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wei Huang , Christopher Covington Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington Reviewed-by: Andrew Jones --- arm/pmu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 42d0ee1..4334de4 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -14,6 +14,8 @@ */ #include "libcflat.h" +#define NR_SAMPLES 10 + #if defined(__arm__) static inline uint32_t get_pmcr(void) { @@ -22,6 +24,25 @@ static inline uint32_t get_pmcr(void) asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret)); return ret; } + +static inline void set_pmcr(uint32_t pmcr) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (pmcr)); +} + +/* + * While PMCCNTR can be accessed as a 64 bit coprocessor register, returning 64 + * bits doesn't seem worth the trouble when differential usage of the result is + * expected (with differences that can easily fit in 32 bits). So just return + * the lower 32 bits of the cycle count in AArch32. + */ +static inline unsigned long get_pmccntr(void) +{ + unsigned long cycles; + + asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (cycles)); + return cycles; +} #elif defined(__aarch64__) static inline uint32_t get_pmcr(void) { @@ -30,6 +51,19 @@ static inline uint32_t get_pmcr(void) asm volatile("mrs %0, pmcr_el0" : "=r" (ret)); return ret; } + +static inline void set_pmcr(uint32_t pmcr) +{ + asm volatile("msr pmcr_el0, %0" : : "r" (pmcr)); +} + +static inline unsigned long get_pmccntr(void) +{ + unsigned long cycles; + + asm volatile("mrs %0, pmccntr_el0" : "=r" (cycles)); + return cycles; +} #endif struct pmu_data { @@ -72,11 +106,37 @@ static bool check_pmcr(void) return pmu.implementer != 0; } +/* + * Ensure that the cycle counter progresses between back-to-back reads. + */ +static bool check_cycles_increase(void) +{ + struct pmu_data pmu = {0}; + + pmu.enable = 1; + set_pmcr(pmu.pmcr_el0); + + for (int i = 0; i < NR_SAMPLES; i++) { + unsigned long a, b; + + a = get_pmccntr(); + b = get_pmccntr(); + + if (a >= b) { + printf("Read %ld then %ld.\n", a, b); + return false; + } + } + + return true; +} + int main(void) { report_prefix_push("pmu"); report("Control register", check_pmcr()); + report("Monotonically increasing cycle count", check_cycles_increase()); return report_summary(); }