From patchwork Thu Nov 17 17:57:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9434953 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 955AF60469 for ; Thu, 17 Nov 2016 17:58:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 880872968C for ; Thu, 17 Nov 2016 17:58:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7CD6E29693; Thu, 17 Nov 2016 17:58:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6C4592968C for ; Thu, 17 Nov 2016 17:58:00 +0000 (UTC) Received: from localhost ([::1]:60689 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qwh-0000e0-KA for patchwork-qemu-devel@patchwork.kernel.org; Thu, 17 Nov 2016 12:57:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43110) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw6-0000bV-U8 for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c7Qw4-0006U9-Ca for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:23 -0500 Received: from foss.arm.com ([217.140.101.70]:37108) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw4-0006TE-3T for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:20 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1DD50152D; Thu, 17 Nov 2016 09:57:19 -0800 (PST) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EEB5F3F220; Thu, 17 Nov 2016 09:57:17 -0800 (PST) From: Andre Przywara To: Andrew Jones Date: Thu, 17 Nov 2016 17:57:49 +0000 Message-Id: <20161117175752.16475-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161117175752.16475-1-andre.przywara@arm.com> References: <20161117175752.16475-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH 1/4] arm/arm64: GIC: basic GICv2 MMIO tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, Christoffer Dall Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This adds an MMIO subtest to the GIC test. It accesses some generic GICv2 registers and does some sanity tests, like checking for some of them being read-only. Signed-off-by: Andre Przywara --- arm/gic.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++++ lib/arm/asm/gic.h | 2 ++ 3 files changed, 107 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 638b8b1..ba2585b 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -3,6 +3,7 @@ * * GICv2 * + test sending/receiving IPIs + * + MMIO access tests * GICv3 * + test sending/receiving IPIs * @@ -274,6 +275,98 @@ static struct gic gicv3 = { }, }; +static bool test_ro_pattern_32(void *address, u32 pattern, u32 orig) +{ + u32 reg; + + writel(pattern, address); + reg = readl(address); + + if (reg != orig) + writel(orig, address); + + return reg == orig; +} + +static bool test_readonly_32(void *address, bool razwi) +{ + u32 orig, pattern; + + orig = readl(address); + if (razwi && orig) + return false; + + pattern = 0xffffffff; + if (orig != pattern) { + if (!test_ro_pattern_32(address, pattern, orig)) + return false; + } + + pattern = 0xa5a55a5a; + if (orig != pattern) { + if (!test_ro_pattern_32(address, pattern, orig)) + return false; + } + + pattern = 0; + if (orig != pattern) { + if (!test_ro_pattern_32(address, pattern, orig)) + return false; + } + + return true; +} + +static bool test_typer_v2(uint32_t reg) +{ + int nr_gic_cpus = ((reg >> 5) & 0x7) + 1; + + report("all %d CPUs have interrupts", nr_cpus == nr_gic_cpus, + nr_gic_cpus); + + return true; +} + +static int gic_test_mmio(int gic_version) +{ + u32 reg; + int nr_irqs; + void *gic_dist_base, *idreg; + + switch(gic_version) { + case 0x2: + gic_dist_base = gicv2_dist_base(); + idreg = gic_dist_base + 0xfe8; + break; + case 0x3: + report_abort("GICv3 MMIO tests NYI"); + return -1; + default: + report_abort("GIC version %d not supported", gic_version); + return 0; + } + + reg = readl(gic_dist_base + GICD_TYPER); + nr_irqs = 32 * ((reg & 0x1f) + 1); + report("number of implemented SPIs: %d", 1, nr_irqs - 32); + + test_typer_v2(reg); + + report("IIDR: 0x%x", 1, readl(gic_dist_base + GICD_IIDR)); + + report("GICD_TYPER is read-only", + test_readonly_32(gic_dist_base + GICD_TYPER, false)); + report("GICD_IIDR is read-only", + test_readonly_32(gic_dist_base + GICD_IIDR, false)); + + reg = readl(idreg); + report("ICPIDR2 is read-only (0x%x)", + test_readonly_32(idreg, false), + reg); + + return 0; +} + int main(int argc, char **argv) { char pfx[8]; @@ -332,6 +425,12 @@ int main(int argc, char **argv) } ipi_test(); + } else if (!strcmp(argv[1], "mmio")) { + report_prefix_push(argv[1]); + + gic_test_mmio(gic_version()); + + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index c7392c7..0162e5a 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -67,6 +67,12 @@ smp = $((($MAX_SMP < 8)?$MAX_SMP:8)) extra_params = -machine gic-version=2 -append 'ipi' groups = gic +[gicv2-mmio] +file = gic.flat +smp = $((($MAX_SMP < 8)?$MAX_SMP:8)) +extra_params = -machine gic-version=2 -append 'mmio' +groups = gic + [gicv3-ipi] file = gic.flat smp = $MAX_SMP diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index c2267b6..cef748d 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -10,10 +10,12 @@ /* Distributor registers */ #define GICD_CTLR 0x0000 #define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 #define GICD_IPRIORITYR 0x0400 #define GICD_SGIR 0x0f00 +#define GICD_ICPIDR2 0x0fe8 #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) #define GICD_INT_EN_SET_SGI 0x0000ffff