From patchwork Thu Nov 17 17:57:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9434973 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB88860469 for ; Thu, 17 Nov 2016 18:03:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0A532960B for ; Thu, 17 Nov 2016 18:03:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D4C4429689; Thu, 17 Nov 2016 18:03:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 937182960B for ; Thu, 17 Nov 2016 18:03:26 +0000 (UTC) Received: from localhost ([::1]:60729 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7R1x-0005D8-QP for patchwork-qemu-devel@patchwork.kernel.org; Thu, 17 Nov 2016 13:03:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw6-0000bU-Th for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c7Qw5-0006V0-6F for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:22 -0500 Received: from foss.arm.com ([217.140.101.70]:37118) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw5-0006Ud-0w for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:21 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CE2916; Thu, 17 Nov 2016 09:57:20 -0800 (PST) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5901F3F220; Thu, 17 Nov 2016 09:57:19 -0800 (PST) From: Andre Przywara To: Andrew Jones Date: Thu, 17 Nov 2016 17:57:50 +0000 Message-Id: <20161117175752.16475-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161117175752.16475-1-andre.przywara@arm.com> References: <20161117175752.16475-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH 2/4] arm/arm64: GICv2: add GICD_IPRIORITYR testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, Christoffer Dall Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Some tests for the IPRIORITY registers. The significant number of bits is IMPLEMENTATION DEFINED, but should be the same for every IRQ. Also these registers must be byte-accessible. Check that accesses beyond the implemented IRQ limit are actually read-as-zero/write-ignore. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- arm/gic.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index ba2585b..a27da2c 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -327,6 +327,76 @@ static bool test_typer_v2(uint32_t reg) return true; } +#define BYTE(reg32, byte) (((reg32) >> ((byte) * 8)) & 0xff) +#define REPLACE_BYTE(reg32, byte, new) (((reg32) & ~(0xff << ((byte) * 8))) |\ + ((new) << ((byte) * 8))) + +static bool test_priorities(int nr_irqs, void *priptr) +{ + u32 orig_prio, reg, pri_bits; + u32 pri_mask, pattern; + + orig_prio = readl(priptr + 32); + report_prefix_push("IPRIORITYR"); + + /* + * Determine implemented number of priority bits by writing all 1's + * and checking the number of cleared bits in the value read back. + */ + writel(0xffffffff, priptr + 32); + pri_mask = readl(priptr + 32); + + reg = ~pri_mask; + report("consistent priority masking (0x%08x)", + (((reg >> 16) == (reg & 0xffff)) && + ((reg & 0xff) == ((reg >> 8) & 0xff))), pri_mask); + + reg = reg & 0xff; + for (pri_bits = 8; reg & 1; reg >>= 1, pri_bits--) + ; + report("implements at least 4 priority bits (%d)", + pri_bits >= 4, pri_bits); + + pattern = 0; + writel(pattern, priptr + 32); + report("clearing priorities", readl(priptr + 32) == pattern); + + pattern = 0xffffffff; + writel(pattern, priptr + 32); + report("filling priorities", + readl(priptr + 32) == (pattern & pri_mask)); + + report("accesses beyond limit RAZ/WI", + test_readonly_32(priptr + nr_irqs, true)); + + writel(pattern, priptr + nr_irqs - 4); + report("accessing last SPIs", + readl(priptr + nr_irqs - 4) == (pattern & pri_mask)); + + pattern = 0xff7fbf3f; + writel(pattern, priptr + 32); + report("priorities are preserved", + readl(priptr + 32) == (pattern & pri_mask)); + + /* + * The PRIORITY registers are byte accessible, do a byte-wide + * read and write of known content to check for this. + */ + reg = readb(priptr + 33); + report("byte reads successful (0x%08x => 0x%02x)", + reg == (BYTE(pattern, 1) & pri_mask), pattern & pri_mask, reg); + + pattern = REPLACE_BYTE(pattern, 2, 0x1f); + writeb(BYTE(pattern, 2), priptr + 34); + reg = readl(priptr + 32); + report("byte writes successful (0x%02x => 0x%08x)", + reg == (pattern & pri_mask), BYTE(pattern, 2) & pri_mask, reg); + + report_prefix_pop(); + writel(orig_prio, priptr + 32); + return true; +} + static int gic_test_mmio(int gic_version) { u32 reg; @@ -364,6 +434,8 @@ static int gic_test_mmio(int gic_version) test_readonly_32(idreg, false), reg); + test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR); + return 0; }