From patchwork Thu Nov 17 17:57:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9435021 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 91A1960755 for ; Thu, 17 Nov 2016 18:11:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8692B2960A for ; Thu, 17 Nov 2016 18:11:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75CC329692; Thu, 17 Nov 2016 18:11:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DDA062968B for ; Thu, 17 Nov 2016 18:11:01 +0000 (UTC) Received: from localhost ([::1]:60784 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7R9J-0002wI-2s for patchwork-qemu-devel@patchwork.kernel.org; Thu, 17 Nov 2016 13:11:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43123) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw7-0000bp-Bf for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c7Qw6-0006WL-Je for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:23 -0500 Received: from foss.arm.com ([217.140.101.70]:37130) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw6-0006W0-E6 for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:22 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC55613D5; Thu, 17 Nov 2016 09:57:21 -0800 (PST) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7D533F220; Thu, 17 Nov 2016 09:57:20 -0800 (PST) From: Andre Przywara To: Andrew Jones Date: Thu, 17 Nov 2016 17:57:51 +0000 Message-Id: <20161117175752.16475-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161117175752.16475-1-andre.przywara@arm.com> References: <20161117175752.16475-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH 3/4] arm/arm64: GICv2: add GICD_ITARGETSR testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, Christoffer Dall Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Some tests for the ITARGETS registers. Bits corresponding to non-existent CPUs must be RAZ/WI. These registers must be byte-accessible, also check that accesses beyond the implemented IRQ limit are actually read-as-zero/write-ignore. Signed-off-by: Andre Przywara --- arm/gic.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic.h | 1 + 2 files changed, 55 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index a27da2c..02b1be1 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -397,6 +397,57 @@ static bool test_priorities(int nr_irqs, void *priptr) return true; } +static bool test_targets(int nr_irqs) +{ + void *targetsptr = gicv2_dist_base() + GICD_ITARGETSR; + u32 orig_targets; + u32 cpu_mask; + u32 pattern, reg; + + orig_targets = readl(targetsptr + 32); + report_prefix_push("ITARGETSR"); + + cpu_mask = (1 << nr_cpus) - 1; + cpu_mask |= cpu_mask << 8; + cpu_mask |= cpu_mask << 16; + + /* Check that bits for non implemented CPUs are RAZ/WI. */ + if (nr_cpus < 8) { + writel(0xffffffff, targetsptr + 32); + report("bits for %d non-existent CPUs masked", + !(readl(targetsptr + 32) & ~cpu_mask), 8 - nr_cpus); + } else { + report_skip("CPU masking (all CPUs implemented)"); + } + + report("accesses beyond limit RAZ/WI", + test_readonly_32(targetsptr + nr_irqs, true)); + + pattern = 0x0103020f; + writel(pattern, targetsptr + 32); + reg = readl(targetsptr + 32); + report("register content preserved (%08x => %08x)", + reg == (pattern & cpu_mask), pattern & cpu_mask, reg); + + /* + * The TARGETS registers are byte accessible, do a byte-wide + * read and write of known content to check for this. + */ + reg = readb(targetsptr + 33); + report("byte reads successful (0x%08x => 0x%02x)", + reg == (BYTE(pattern, 1) & cpu_mask), + pattern & cpu_mask, reg); + + pattern = REPLACE_BYTE(pattern, 2, 0x04); + writeb(BYTE(pattern, 2), targetsptr + 34); + reg = readl(targetsptr + 32); + report("byte writes successful (0x%02x => 0x%08x)", + reg == (pattern & cpu_mask), BYTE(pattern, 2), reg); + + writel(orig_targets, targetsptr + 32); + return true; +} + static int gic_test_mmio(int gic_version) { u32 reg; @@ -436,6 +487,9 @@ static int gic_test_mmio(int gic_version) test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR); + if (gic_version == 2) + test_targets(nr_irqs); + return 0; } diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index cef748d..6f170cb 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -14,6 +14,7 @@ #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 #define GICD_IPRIORITYR 0x0400 +#define GICD_ITARGETSR 0x0800 #define GICD_SGIR 0x0f00 #define GICD_ICPIDR2 0x0fe8