From patchwork Thu Nov 17 17:57:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9434965 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 555EE60469 for ; Thu, 17 Nov 2016 18:02:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49A062955E for ; Thu, 17 Nov 2016 18:02:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E30E2966A; Thu, 17 Nov 2016 18:02:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AEA5B2955E for ; Thu, 17 Nov 2016 18:02:25 +0000 (UTC) Received: from localhost ([::1]:60719 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7R0y-0004RA-4t for patchwork-qemu-devel@patchwork.kernel.org; Thu, 17 Nov 2016 13:02:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw8-0000dH-O6 for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c7Qw7-0006Xy-UU for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:24 -0500 Received: from foss.arm.com ([217.140.101.70]:37140) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Qw7-0006XR-Py for qemu-devel@nongnu.org; Thu, 17 Nov 2016 12:57:23 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4701C152D; Thu, 17 Nov 2016 09:57:23 -0800 (PST) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 247FE3F220; Thu, 17 Nov 2016 09:57:22 -0800 (PST) From: Andre Przywara To: Andrew Jones Date: Thu, 17 Nov 2016 17:57:52 +0000 Message-Id: <20161117175752.16475-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161117175752.16475-1-andre.przywara@arm.com> References: <20161117175752.16475-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH 4/4] arm/arm64: GICv3: add TYPER test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, Christoffer Dall Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add a simple test for the GICv3 TYPER test, which does only one basic check to ensure we have actually enough interrupt IDs if we support LPIs. Allow a GICv3 guest to do the common MMIO checks as well, where the register semantics are shared with a GICv2. Signed-off-by: Andre Przywara --- arm/gic.c | 34 +++++++++++++++++++++++++++++++--- arm/unittests.cfg | 6 ++++++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 02b1be1..7de0e47 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -327,6 +327,30 @@ static bool test_typer_v2(uint32_t reg) return true; } +static bool test_typer_v3(uint32_t reg) +{ + int nr_intids; + + report("GIC emulation %ssupport%s MBIs", 1, + reg & BIT(16) ? "" : "does not ", + reg & BIT(16) ? "s" : ""); + report("GIC emulation %ssupport%s LPIs", 1, + reg & BIT(17) ? "" : "does not ", + reg & BIT(17) ? "s" : ""); + report("GIC emulation %ssupport%s Aff3", 1, + reg & BIT(24) ? "" : "does not ", + reg & BIT(24) ? "s" : ""); + + nr_intids = BIT(((reg >> 19) & 0x1f) + 1); + report("%d interrupt IDs implemented", 1, nr_intids); + + if (reg & BIT(17)) + report("%d LPIs supported", nr_intids > 8192, + nr_intids > 8192 ? nr_intids - 8192 : 0); + + return true; +} + #define BYTE(reg32, byte) (((reg32) >> ((byte) * 8)) & 0xff) #define REPLACE_BYTE(reg32, byte, new) (((reg32) & ~(0xff << ((byte) * 8))) |\ ((new) << ((byte) * 8))) @@ -460,8 +484,9 @@ static int gic_test_mmio(int gic_version) idreg = gic_dist_base + 0xfe8; break; case 0x3: - report_abort("GICv3 MMIO tests NYI"); - return -1; + gic_dist_base = gicv3_dist_base(); + idreg = gic_dist_base + 0xffe8; + break; default: report_abort("GIC version %d not supported", gic_version); return 0; @@ -471,7 +496,10 @@ static int gic_test_mmio(int gic_version) nr_irqs = 32 * ((reg & 0x1f) + 1); report("number of implemented SPIs: %d", 1, nr_irqs - 32); - test_typer_v2(reg); + if (gic_version == 2) + test_typer_v2(reg); + else + test_typer_v3(reg); report("IIDR: 0x%x", 1, readl(gic_dist_base + GICD_IIDR)); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 0162e5a..b432346 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -78,3 +78,9 @@ file = gic.flat smp = $MAX_SMP extra_params = -machine gic-version=3 -append 'ipi' groups = gic + +[gicv3-mmio] +file = gic.flat +smp = $MAX_SMP +extra_params = -machine gic-version=3 -append 'mmio' +groups = gic