From patchwork Sat May 13 09:32:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 9725077 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 13EFF60325 for ; Sat, 13 May 2017 09:40:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 08F69288CB for ; Sat, 13 May 2017 09:40:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF35F288D2; Sat, 13 May 2017 09:40:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 680C1288CB for ; Sat, 13 May 2017 09:40:45 +0000 (UTC) Received: from localhost ([::1]:56854 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d9TXY-0002b5-0r for patchwork-qemu-devel@patchwork.kernel.org; Sat, 13 May 2017 05:40:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37131) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d9TQC-0005Ay-6Z for qemu-devel@nongnu.org; Sat, 13 May 2017 05:33:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d9TQA-0001Ls-Qu for qemu-devel@nongnu.org; Sat, 13 May 2017 05:33:08 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:43778) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d9TQA-0001HF-Hk for qemu-devel@nongnu.org; Sat, 13 May 2017 05:33:06 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1d9TQ7-0002Az-K7; Sat, 13 May 2017 11:33:03 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1d9TQ3-0004lE-Fl; Sat, 13 May 2017 11:32:59 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 13 May 2017 11:32:36 +0200 Message-Id: <20170513093248.18230-4-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170513093248.18230-1-aurelien@aurel32.net> References: <20170513093248.18230-1-aurelien@aurel32.net> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 03/15] target/sh4: do not include DELAY_SLOT_TRUE in the TB state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Stefan Hajnoczi Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP DELAY_SLOT_TRUE is used as a dynamic condition for the branch after the delay slot instruction. It is not used in code generation, so there is no need to including in the TB state. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target/sh4/cpu.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9445cc779f..da8d15f1b9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -382,8 +382,7 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, { *pc = env->pc; *cs_base = 0; - *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL - | DELAY_SLOT_TRUE)) /* Bits 0- 2 */ + *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) /* Bits 0-1 */ | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */