| Message ID | 20170817230114.3655-3-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Richard Henderson <richard.henderson@linaro.org> writes: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/translate-a64.c | 137 ++++++++++++++++++++++++++++----------------- > 1 file changed, 87 insertions(+), 50 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 2200e25be0..025354f983 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -21,6 +21,7 @@ > #include "cpu.h" > #include "exec/exec-all.h" > #include "tcg-op.h" > +#include "tcg-op-gvec.h" > #include "qemu/log.h" > #include "arm_ldst.h" > #include "translate.h" > @@ -82,6 +83,7 @@ typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); > typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); > typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); > typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); > +typedef void GVecGenTwoFn(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); > > /* initialize TCG globals. */ > void a64_translate_init(void) > @@ -537,6 +539,21 @@ static inline int vec_reg_offset(DisasContext *s, int regno, > return offs; > } > > +/* Return the offset info CPUARMState of the "whole" vector register Qn. */ > +static inline int vec_full_reg_offset(DisasContext *s, int regno) > +{ > + assert_fp_access_checked(s); > + return offsetof(CPUARMState, vfp.regs[regno * 2]); > +} > + > +/* Return the byte size of the "whole" vector register, VL / 8. */ > +static inline int vec_full_reg_size(DisasContext *s) > +{ > + /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags. > + In the meantime this is just the AdvSIMD length of 128. */ > + return 128 / 8; > +} > + > /* Return the offset into CPUARMState of a slice (from > * the least significant end) of FP register Qn (ie > * Dn, Sn, Hn or Bn). > @@ -9042,11 +9059,38 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) > bool is_q = extract32(insn, 30, 1); > TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; > int pass; > + GVecGenTwoFn *gvec_op; > > if (!fp_access_check(s)) { > return; > } > > + switch (size + 4 * is_u) { Hmm I find this switch a little too magical. I mean I can see that the encoding abuses size for the final opcode when I look at the manual but it reads badly. > + case 0: /* AND */ > + gvec_op = tcg_gen_gvec_and8; > + goto do_gvec; > + case 1: /* BIC */ > + gvec_op = tcg_gen_gvec_andc8; > + goto do_gvec; > + case 2: /* ORR */ > + gvec_op = tcg_gen_gvec_or8; > + goto do_gvec; > + case 3: /* ORN */ > + gvec_op = tcg_gen_gvec_orc8; > + goto do_gvec; > + case 4: /* EOR */ > + gvec_op = tcg_gen_gvec_xor8; > + goto do_gvec; > + do_gvec: > + gvec_op(vec_full_reg_offset(s, rd), > + vec_full_reg_offset(s, rn), > + vec_full_reg_offset(s, rm), > + is_q ? 16 : 8, vec_full_reg_size(s)); > + return; No default case (although I guess we just fall through). What's wrong with just having a !is_u test with gvec_op = tbl[size] and skipping all the goto stuff? > + } > + > + /* Note that we've now eliminated all !is_u. */ > + > tcg_op1 = tcg_temp_new_i64(); > tcg_op2 = tcg_temp_new_i64(); > tcg_res[0] = tcg_temp_new_i64(); > @@ -9056,47 +9100,27 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) > read_vec_element(s, tcg_op1, rn, pass, MO_64); > read_vec_element(s, tcg_op2, rm, pass, MO_64); > > - if (!is_u) { > - switch (size) { > - case 0: /* AND */ > - tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); > - break; > - case 1: /* BIC */ > - tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); > - break; > - case 2: /* ORR */ > - tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); > - break; > - case 3: /* ORN */ > - tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); > - break; > - } > - } else { > - if (size != 0) { > - /* B* ops need res loaded to operate on */ > - read_vec_element(s, tcg_res[pass], rd, pass, MO_64); > - } > + /* B* ops need res loaded to operate on */ > + read_vec_element(s, tcg_res[pass], rd, pass, MO_64); > > - switch (size) { > - case 0: /* EOR */ > - tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); > - break; > - case 1: /* BSL bitwise select */ > - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); > - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); > - tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); > - break; > - case 2: /* BIT, bitwise insert if true */ > - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); > - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); > - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); > - break; > - case 3: /* BIF, bitwise insert if false */ > - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); > - tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); > - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); > - break; > - } > + switch (size) { > + case 1: /* BSL bitwise select */ > + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); > + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); > + tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); > + break; > + case 2: /* BIT, bitwise insert if true */ > + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); > + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); > + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); > + break; > + case 3: /* BIF, bitwise insert if false */ > + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); > + tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); > + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); > + break; > + default: > + g_assert_not_reached(); > } > } > > @@ -9370,6 +9394,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) > int rn = extract32(insn, 5, 5); > int rd = extract32(insn, 0, 5); > int pass; > + GVecGenTwoFn *gvec_op; > > switch (opcode) { > case 0x13: /* MUL, PMUL */ > @@ -9409,6 +9434,28 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) > return; > } > > + switch (opcode) { > + case 0x10: /* ADD, SUB */ > + { > + static GVecGenTwoFn * const fns[4][2] = { > + { tcg_gen_gvec_add8, tcg_gen_gvec_sub8 }, > + { tcg_gen_gvec_add16, tcg_gen_gvec_sub16 }, > + { tcg_gen_gvec_add32, tcg_gen_gvec_sub32 }, > + { tcg_gen_gvec_add64, tcg_gen_gvec_sub64 }, > + }; > + gvec_op = fns[size][u]; > + goto do_gvec; > + } > + break; > + > + do_gvec: > + gvec_op(vec_full_reg_offset(s, rd), > + vec_full_reg_offset(s, rn), > + vec_full_reg_offset(s, rm), > + is_q ? 16 : 8, vec_full_reg_size(s)); > + return; > + } > + > if (size == 3) { > assert(is_q); > for (pass = 0; pass < 2; pass++) { > @@ -9581,16 +9628,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) > genfn = fns[size][u]; > break; > } > - case 0x10: /* ADD, SUB */ > - { > - static NeonGenTwoOpFn * const fns[3][2] = { > - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, > - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, > - { tcg_gen_add_i32, tcg_gen_sub_i32 }, > - }; > - genfn = fns[size][u]; > - break; > - } > case 0x11: /* CMTST, CMEQ */ > { > static NeonGenTwoOpFn * const fns[3][2] = { Other than the comments on the switch the rest looks good to me. -- Alex Bennée
On 09/07/2017 09:58 AM, Alex Bennée wrote: >> + switch (size + 4 * is_u) { > > Hmm I find this switch a little too magical. I mean I can see that the > encoding abuses size for the final opcode when I look at the manual but > it reads badly. > >> + case 0: /* AND */ >> + gvec_op = tcg_gen_gvec_and8; >> + goto do_gvec; >> + case 1: /* BIC */ >> + gvec_op = tcg_gen_gvec_andc8; >> + goto do_gvec; >> + case 2: /* ORR */ >> + gvec_op = tcg_gen_gvec_or8; >> + goto do_gvec; >> + case 3: /* ORN */ >> + gvec_op = tcg_gen_gvec_orc8; >> + goto do_gvec; >> + case 4: /* EOR */ >> + gvec_op = tcg_gen_gvec_xor8; >> + goto do_gvec; >> + do_gvec: >> + gvec_op(vec_full_reg_offset(s, rd), >> + vec_full_reg_offset(s, rn), >> + vec_full_reg_offset(s, rm), >> + is_q ? 16 : 8, vec_full_reg_size(s)); >> + return; > > No default case (although I guess we just fall through). What's wrong > with just having a !is_u test with gvec_op = tbl[size] and skipping all > the goto stuff? Because that would still leave EOR out in the woods. I do think this is the cleanest way to filter out these 5 operations. r~
Richard Henderson <richard.henderson@linaro.org> writes: > On 09/07/2017 09:58 AM, Alex Bennée wrote: >>> + switch (size + 4 * is_u) { >> >> Hmm I find this switch a little too magical. I mean I can see that the >> encoding abuses size for the final opcode when I look at the manual but >> it reads badly. >> >>> + case 0: /* AND */ >>> + gvec_op = tcg_gen_gvec_and8; >>> + goto do_gvec; >>> + case 1: /* BIC */ >>> + gvec_op = tcg_gen_gvec_andc8; >>> + goto do_gvec; >>> + case 2: /* ORR */ >>> + gvec_op = tcg_gen_gvec_or8; >>> + goto do_gvec; >>> + case 3: /* ORN */ >>> + gvec_op = tcg_gen_gvec_orc8; >>> + goto do_gvec; >>> + case 4: /* EOR */ >>> + gvec_op = tcg_gen_gvec_xor8; >>> + goto do_gvec; >>> + do_gvec: >>> + gvec_op(vec_full_reg_offset(s, rd), >>> + vec_full_reg_offset(s, rn), >>> + vec_full_reg_offset(s, rm), >>> + is_q ? 16 : 8, vec_full_reg_size(s)); >>> + return; >> >> No default case (although I guess we just fall through). What's wrong >> with just having a !is_u test with gvec_op = tbl[size] and skipping all >> the goto stuff? > > Because that would still leave EOR out in the woods. > I do think this is the cleanest way to filter out these 5 operations. Is this going to look better if the other operations in this branch of the decode are converted as well? -- Alex Bennée
On 09/11/2017 02:12 AM, Alex Bennée wrote: > > Richard Henderson <richard.henderson@linaro.org> writes: > >> On 09/07/2017 09:58 AM, Alex Bennée wrote: >>>> + switch (size + 4 * is_u) { >>> >>> Hmm I find this switch a little too magical. I mean I can see that the >>> encoding abuses size for the final opcode when I look at the manual but >>> it reads badly. >>> >>>> + case 0: /* AND */ >>>> + gvec_op = tcg_gen_gvec_and8; >>>> + goto do_gvec; >>>> + case 1: /* BIC */ >>>> + gvec_op = tcg_gen_gvec_andc8; >>>> + goto do_gvec; >>>> + case 2: /* ORR */ >>>> + gvec_op = tcg_gen_gvec_or8; >>>> + goto do_gvec; >>>> + case 3: /* ORN */ >>>> + gvec_op = tcg_gen_gvec_orc8; >>>> + goto do_gvec; >>>> + case 4: /* EOR */ >>>> + gvec_op = tcg_gen_gvec_xor8; >>>> + goto do_gvec; >>>> + do_gvec: >>>> + gvec_op(vec_full_reg_offset(s, rd), >>>> + vec_full_reg_offset(s, rn), >>>> + vec_full_reg_offset(s, rm), >>>> + is_q ? 16 : 8, vec_full_reg_size(s)); >>>> + return; >>> >>> No default case (although I guess we just fall through). What's wrong >>> with just having a !is_u test with gvec_op = tbl[size] and skipping all >>> the goto stuff? >> >> Because that would still leave EOR out in the woods. >> I do think this is the cleanest way to filter out these 5 operations. > > Is this going to look better if the other operations in this branch of > the decode are converted as well? It might do. I'll have to think about those some more. Indeed, perhaps that's exactly what I ought to do. Those are complex logical operations which certainly will not get their own opcodes, but are "simple" in that they can be implemented in terms of vector xor+and, so there's no reason we couldn't expand those inline for all vector supporting hosts. r~
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2200e25be0..025354f983 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/log.h" #include "arm_ldst.h" #include "translate.h" @@ -82,6 +83,7 @@ typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); +typedef void GVecGenTwoFn(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); /* initialize TCG globals. */ void a64_translate_init(void) @@ -537,6 +539,21 @@ static inline int vec_reg_offset(DisasContext *s, int regno, return offs; } +/* Return the offset info CPUARMState of the "whole" vector register Qn. */ +static inline int vec_full_reg_offset(DisasContext *s, int regno) +{ + assert_fp_access_checked(s); + return offsetof(CPUARMState, vfp.regs[regno * 2]); +} + +/* Return the byte size of the "whole" vector register, VL / 8. */ +static inline int vec_full_reg_size(DisasContext *s) +{ + /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags. + In the meantime this is just the AdvSIMD length of 128. */ + return 128 / 8; +} + /* Return the offset into CPUARMState of a slice (from * the least significant end) of FP register Qn (ie * Dn, Sn, Hn or Bn). @@ -9042,11 +9059,38 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) bool is_q = extract32(insn, 30, 1); TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; int pass; + GVecGenTwoFn *gvec_op; if (!fp_access_check(s)) { return; } + switch (size + 4 * is_u) { + case 0: /* AND */ + gvec_op = tcg_gen_gvec_and8; + goto do_gvec; + case 1: /* BIC */ + gvec_op = tcg_gen_gvec_andc8; + goto do_gvec; + case 2: /* ORR */ + gvec_op = tcg_gen_gvec_or8; + goto do_gvec; + case 3: /* ORN */ + gvec_op = tcg_gen_gvec_orc8; + goto do_gvec; + case 4: /* EOR */ + gvec_op = tcg_gen_gvec_xor8; + goto do_gvec; + do_gvec: + gvec_op(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + } + + /* Note that we've now eliminated all !is_u. */ + tcg_op1 = tcg_temp_new_i64(); tcg_op2 = tcg_temp_new_i64(); tcg_res[0] = tcg_temp_new_i64(); @@ -9056,47 +9100,27 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) read_vec_element(s, tcg_op1, rn, pass, MO_64); read_vec_element(s, tcg_op2, rm, pass, MO_64); - if (!is_u) { - switch (size) { - case 0: /* AND */ - tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BIC */ - tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 2: /* ORR */ - tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 3: /* ORN */ - tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - } - } else { - if (size != 0) { - /* B* ops need res loaded to operate on */ - read_vec_element(s, tcg_res[pass], rd, pass, MO_64); - } + /* B* ops need res loaded to operate on */ + read_vec_element(s, tcg_res[pass], rd, pass, MO_64); - switch (size) { - case 0: /* EOR */ - tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BSL bitwise select */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); - break; - case 2: /* BIT, bitwise insert if true */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - case 3: /* BIF, bitwise insert if false */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - } + switch (size) { + case 1: /* BSL bitwise select */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); + break; + case 2: /* BIT, bitwise insert if true */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + break; + case 3: /* BIF, bitwise insert if false */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + break; + default: + g_assert_not_reached(); } } @@ -9370,6 +9394,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); int pass; + GVecGenTwoFn *gvec_op; switch (opcode) { case 0x13: /* MUL, PMUL */ @@ -9409,6 +9434,28 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) return; } + switch (opcode) { + case 0x10: /* ADD, SUB */ + { + static GVecGenTwoFn * const fns[4][2] = { + { tcg_gen_gvec_add8, tcg_gen_gvec_sub8 }, + { tcg_gen_gvec_add16, tcg_gen_gvec_sub16 }, + { tcg_gen_gvec_add32, tcg_gen_gvec_sub32 }, + { tcg_gen_gvec_add64, tcg_gen_gvec_sub64 }, + }; + gvec_op = fns[size][u]; + goto do_gvec; + } + break; + + do_gvec: + gvec_op(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + } + if (size == 3) { assert(is_q); for (pass = 0; pass < 2; pass++) { @@ -9581,16 +9628,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn = fns[size][u]; break; } - case 0x10: /* ADD, SUB */ - { - static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, - { tcg_gen_add_i32, tcg_gen_sub_i32 }, - }; - genfn = fns[size][u]; - break; - } case 0x11: /* CMTST, CMEQ */ { static NeonGenTwoOpFn * const fns[3][2] = {
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-a64.c | 137 ++++++++++++++++++++++++++++----------------- 1 file changed, 87 insertions(+), 50 deletions(-)