From patchwork Tue Aug 29 06:33:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pranith Kumar X-Patchwork-Id: 9926793 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E4C236022E for ; Tue, 29 Aug 2017 06:34:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D198928885 for ; Tue, 29 Aug 2017 06:34:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C6AFE28887; Tue, 29 Aug 2017 06:34:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E678228886 for ; Tue, 29 Aug 2017 06:34:43 +0000 (UTC) Received: from localhost ([::1]:43059 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dma6l-0000Qr-7X for patchwork-qemu-devel@patchwork.kernel.org; Tue, 29 Aug 2017 02:34:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dma5R-0000P6-LF for qemu-devel@nongnu.org; Tue, 29 Aug 2017 02:33:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dma5Q-00042Q-Ia for qemu-devel@nongnu.org; Tue, 29 Aug 2017 02:33:21 -0400 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34754) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dma5Q-00042L-Do for qemu-devel@nongnu.org; Tue, 29 Aug 2017 02:33:20 -0400 Received: by mail-yw0-x242.google.com with SMTP id h127so1495652ywf.1 for ; Mon, 28 Aug 2017 23:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7jf5kKveFFHMo0yJcrJ1liN+nMs1p848URNjXj7SZxg=; b=vY3KGb8lNeYKpI45nYNSYVMl2ecsk703DU6vJXrfVB+YQiSPBQ7g+dh7tOoXn9hBXS GaI8erj7DchQLPtR3cJwZPvLMs85McgACY0aHO9I8KImu7b6Bw1YMvfHCHmh53Tp3p3c iXO+SG+egDCtNimfSea7YKjLOZ8wRfjyG6pisTn/M7WaU/q4rw4pdr2ly7O3OQl0SX1W QcwbeuY0TyB4skpFLecKrhTN8Ce0YXx6nTPBF/anamoZNmEenEWYW99rjxQTaorQBHYt wldroo2aZ7RmN/wu3kHXLZfR1J4wM+JoChhjro04GBh8ByTLHL4osgxfuxGQUKp/Rpvp yaMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7jf5kKveFFHMo0yJcrJ1liN+nMs1p848URNjXj7SZxg=; b=Fds9VRClE8nt8E4XD312BXcnVQ0k0f1ILTaU16CS0NChRfuUyf4HpKLFwqKs0aFJEj 6CXEgoQRfbRG5+W8CySzr1atwNHK/R4js4Ml0FImXuZRl2obv8Xn5W846h8EKzNExm3S 6bd148fRzmalzmEBCgzpqYDOXdkzWFHoJAyhPl0Z/rfX+0lWVj9sfSxrPnWlrlAsCbFn pnuFnJuYjdbIlQZ30Yt3PmVb+3Jw0am2LHysxsU5ZGCuORabbGGnkPxgL3fDsXhLlMPI bDhEdD/y6fwvsKnatwF1uvvvMbkOBVg2O0Cc5FBkrYuSLK65VQcaZXctIi97oXZqQDUE Hkcg== X-Gm-Message-State: AHYfb5hcogdcQ6Z/TViZGpZIHFWK+4rwfs9whWlLXHXlX7uv0Q8y+GX6 6XQLtZIqOcSX0Q== X-Received: by 10.13.204.131 with SMTP id o125mr2509450ywd.388.1503988399722; Mon, 28 Aug 2017 23:33:19 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id x4sm817923ywa.44.2017.08.28.23.33.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 23:33:18 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org, Richard Henderson , qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 29 Aug 2017 02:33:12 -0400 Message-Id: <20170829063313.10237-4-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170829063313.10237-1-bobby.prani@gmail.com> References: <20170829063313.10237-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::242 Subject: [Qemu-devel] [RFC v3 PATCH 4/5] mttcg: Implement implicit ordering semantics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently, we cannot use mttcg for running strong memory model guests on weak memory model hosts due to missing ordering semantics. We implicitly generate fence instructions for stronger guests if an ordering mismatch is detected. We generate fences only for the orders for which fence instructions are necessary, for example a fence is not necessary between a store and a subsequent load on x86 since its absence in the guest binary tells that ordering need not be ensured. Also note that if we find multiple subsequent fence instructions in the generated IR, we combine them in the TCG optimization pass. This patch allows us to boot an x86 guest on ARM64 hosts using mttcg. Signed-off-by: Pranith Kumar Reviewed-by: Richard Henderson --- tcg/tcg-op.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673ef49..688d91755b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,6 +28,7 @@ #include "exec/exec-all.h" #include "tcg.h" #include "tcg-op.h" +#include "tcg-mo.h" #include "trace-tcg.h" #include "trace/mem.h" @@ -2662,8 +2663,20 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, #endif } +static void tcg_gen_req_mo(TCGBar type) +{ +#ifdef TCG_GUEST_DEFAULT_MO + type &= TCG_GUEST_DEFAULT_MO; +#endif + type &= ~TCG_TARGET_DEFAULT_MO; + if (type) { + tcg_gen_mb(type | TCG_BAR_SC); + } +} + void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 0)); @@ -2672,6 +2685,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 1)); @@ -2680,6 +2694,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2698,6 +2713,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return;