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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:53 -0700 Message-Id: <20170906160612.22769-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 13/32] target/i386: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002243497.22386.8888053391875656102.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 9872f84a03..ad4b2735f4 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8518,6 +8518,21 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) } } +static void i386_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + int disas_flags = !dc->code32; + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); +#ifdef TARGET_X86_64 + if (dc->code64) { + disas_flags = 2; + } +#endif + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8593,28 +8608,19 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_io_end(); gen_tb_end(tb, num_insns); + tb->size = dc->base.pc_next - dc->base.pc_first; + tb->icount = num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { - int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); -#ifdef TARGET_X86_64 - if (dc->code64) - disas_flags = 2; - else -#endif - disas_flags = !dc->code32; - log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->base.pc_first, - disas_flags); + i386_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - - tb->size = dc->base.pc_next - dc->base.pc_first; - tb->icount = num_insns; } void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,